AD9518_2_15 Datasheet, PDF (25/64 Pages) Analog Devices – 6-Output Clock Generator with Integrated 2.2 GHz VCO

Data Sheet
REF_ SEL
VS GND
RSET
REFMON
REFIN (REF1)
REFIN (REF2)
BYPASS
LF
CLK
CLK
PD
SYNC
RESET
REF1
REF2
REFERENCE
SWITCHOVER
STATUS
STATUS
LOW DROPOUT
REGULATOR (LDO)
VCO
DIGITAL
LOGIC
DISTRIBUTION
REFERENCE
R
DIVIDER
VCO STATUS
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
PROGRAMMABLE
R DELAY
PROGRAMMABLE
N DELAY
DIVIDE BY
2, 3, 4, 5, OR 6
10
DIVIDE BY
1 TO 32
SCLK
SDIO
SDO
CS
SERIAL
CONTROL
PORT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
AD9518-2
CPRSET VCP
AD9518-2
LD
LOCK
DETECT
HOLD
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
STATUS
LVPECL
LVPECL
LVPECL
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
Figure 30. Clock Distribution or External VCO < 1600 MHz
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is less than 1600 MHz, a configuration that bypasses
the VCO divider can be used. This configuration differs from the
High Frequency Clock Distribution—CLK or External VCO >
1600 MHz section only in that the VCO divider (divide-by-2/
divide-by-3/divide-by-4/divide-by-5/divide-by-6) is bypassed.
This limits the frequency of the clock source to <1600 MHz (due
to the maximum input frequency allowed at the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
less than 1600 MHz, use the register settings shown in Table 24.
Table 25. Settings for Using Internal PLL with External VCO <
1600 MHz
Register
Function
0x1E1[0] = 1b
Bypass the VCO divider as source for distribution
section
0x010[1:0] = 00b PLL normal operation (PLL on), along with
other appropriate PLL settings in Register 0x010
to Register 0x01D
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 24. Settings for Clock Distribution < 1600 MHz
Register
Function
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off )
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
0x1E1[1] = 0b
CLK selected as the source
When using the internal PLL with an external VCO of <1600 MHz,
the PLL must be turned on.
Table 26. Setting the PFD Polarity
Register
Function
0x010[7] = 0b
PFD polarity positive (higher control voltage
produces higher frequency)
0x010[7] = 1b
PFD polarity negative (higher control voltage
produces lower frequency)
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Rev. C | Page 25 of 64