ADSP-BF534_08 Datasheet, PDF (55/68 Pages) Analog Devices – Blackfin Embedded Processor

and I_L is the total leakage or three-state current (per data line).
The hold time is t_DECAY plus the minimum disable time (for
example, t_DSDAT for an SDRAM write cycle).
TO
OUTPUT
PIN
50⍀
30pF
V_LOAD
Figure 47. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
INPUT
OR
OUTPUT
V_MEAS
V_{M E A S}
Figure 48. Voltage Reference Levels for AC Measurements (Except
Output Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 47). Figure 49 through Figure 58 on
Page 57 show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
14
12
RISE TIME
10
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 49. Typical Output Delay or Hold for Driver A at V_DDEXT Min
ADSP-BF534/ADSP-BF536/ADSP-BF537
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 50. Typical Output Delay or Hold for Driver A at V_DDEXT Max
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 51. Typical Output Delay or Hold for Driver B at V_DDEXT Min
Rev. E | Page 55 of 68 | March 2008