ADSP-BF534_08 Datasheet, PDF (33/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF534/ADSP-BF536/ADSP-BF537
External Port Bus Request and Grant Cycle Timing
Table 25 and Figure 12 describe external port bus request and
bus grant operations.
Table 25. External Port Bus Request and Grant Cycle Timing
Parameter^{1, 2}
Timing Requirements
t_BS
BR Asserted to CLKOUT Low Setup
t_BH
CLKOUT Low to BR Deasserted Hold Time
Switching Characteristics
t_SD
CLKOUT Low to AMSx, Address, and ARE/AWE Disable
t_SE
CLKOUT Low to AMSx, Address, and ARE/AWE Enable
t_DBG
CLKOUT High to BG Asserted Setup
t_EBG
CLKOUT High to BG Deasserted Hold Time
t_DBH
CLKOUT High to BGH Asserted Setup
t_EBH
CLKOUT High to BGH Deasserted Hold Time
1 _{These are preliminary timing parameters that are based on worst-case operating conditions.}
2 _{The pad loads for these timing parameters are 20 pF.}
Min
Max
Unit
4.6
ns
0.0
ns
4.5
ns
4.5
ns
3.6
ns
3.6
ns
3.6
ns
3.6
ns
CLKOUT
BR
AMSx
ADDR19-1
ABE1-0
AWE
ARE
BG
BGH
t_BS
t_BH
t_SD
t_SD
t_SD
t_DBG
t_DBH
Figure 12. External Port Bus Request and Grant Cycle Timing
t_SE
t_SE
t_SE
t_EBG
t_EBH
Rev. E | Page 33 of 68 | March 2008