ADSP-BF523_15 Datasheet, PDF (55/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE
t_SCLKIW
RSCLKx
SAMPLE EDGE
t_HOFSI
RFSx
(OUTPUT)
t_DFSI
RFSx
(INPUT)
t_SFSI
t_HFSI
DRx
t_SDRI
t_HDRI
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
t_SCLKEW
t_SCLKE
RSCLKx
t_HOFSE
RFSx
(OUTPUT)
t_DFSE
RFSx
(INPUT)
t_SFSE
t_HFSE
DRx
t_SDRE
t_HDRE
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE
t_SCLKIW
TSCLKx
SAMPLE EDGE
t_HOFSI
TFSx
(OUTPUT)
t_{D FSI}
TFSx
(INPUT)
DTx
t_HDTI
t_DDTI
t_SFSI
t_HFSI
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
t_SCLKE
t SCLKEW
TSCLKx
t_HOFSE
TFSx
(OUTPUT)
t_DFSE
TFSx
(INPUT)
DTx
t_HDTE
t_DDTE
t_SFSE
t_HFSE
Figure 24. Serial Ports
TSCLKx
(INPUT)
TFSx
(INPUT)
t_SUDTE
RSCLKx
(INPUT)
RFSx
(INPUT)
t_SUDRE
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED
Figure 25. Serial Port Start Up with External Clock and Frame Sync
Rev. D | Page 55 of 88 | July 2013