ADSP-BF523_15 Datasheet, PDF (53/88 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Serial Ports
Table 43 through Table 47 on Page 57 and Figure 24 on Page 55
through Figure 27 on Page 57 describe serial port operations.
Table 43. Serial Ports—External Clock
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
V_DDEXT
1.8V Nominal
Parameter
Min
Max
Timing Requirements
t_SFSE TFSx/RFSx Setup Before TSCLKx RSCLKx¹ 3.0
t_HFSE TFSx/RFSx Hold After TSCLKx/RSCLKx¹ 3.0
t_SDRE Receive Data Setup Before RSCLKx¹ 3.0
t_HDRE Receive Data Hold After RSCLKx¹
3.5
t_SCLKEW TSCLKx/RSCLKx Width
7.0
t_SCLKE TSCLKx/RSCLKx Period
2.0 × t_SCLK
t_SUDTE Start-Up Delay From SPORT Enable To 4.0 × t_SCLKE
First External TFSx²
t_SUDRE Start-Up Delay From SPORT Enable To 4.0 × t_SCLKE
First External RFSx²
Switching Characteristics
t_DFSE TFSx/RFSx Delay After TSCLKx/RSCLKx
10.0
(Internally Generated TFSx/RFSx)³
t_HOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx 0.0
(Internally Generated TFSx/RFSx)³
t_DDTE Transmit Data Delay After TSCLKx³
10.0
t_HDTE Transmit Data Hold After TSCLKx³
0.0
1 _{Referenced to sample edge.}
2 _{Verified in design but untested.}
3 _{Referenced to drive edge.}
V_DDEXT
2.5 V or 3.3V
Nominal
Min
Max
3.0
3.0
3.0
3.0
4.5
2.0 × t_SCLK
4.0 × t_SCLKE
4.0 × t_SCLKE
10.0
0.0
10.0
0.0
V_DDEXT
1.8V Nominal
Min
Max
V_DDEXT
2.5 V or 3.3V
Nominal
Min
Max
3.0
3.0
3.0
3.5
7.0
2.0 × t_SCLK
4.0 × t_SCLKE
4.0 × t_SCLKE
3.0
3.0
3.0
3.0
4.5
2.0 × t_SCLK
4.0 × t_SCLKE
4.0 × t_SCLKE
10.0
10.0
0.0
0.0
10.0
10.0
0.0
0.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. D | Page 53 of 88 | July 2013