ADSP-BF512BBCZ-4F4 Datasheet, PDF (53/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Output Disable Time Measurement
Output signals are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay from
their output high or low voltage. The output disable time t_DIS is
the difference between t_{DIS_MEASURED} and t_DECAY as shown on the
left side of Figure 54.
t_DIS = t_{DIS_MEASURED} – t_DECAY
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load C_L and the load current I_L. This decay
time can be approximated by the equation:
t_DECAY = (C_LΔV) ⁄ I_L
The time t_DECAY is calculated with test loads C_L and I_L and with
ΔV equal to 0.25 V for V_DDEXT/V_DDMEM (nominal) = 2.5 V/3.3 V
and 0.15 V for V_DDEXT/_VDDMEM (nominal) = 1.8 V.
The time t_{DIS_MEASURED} is the interval from when the reference
signal switches to when the output voltage decays ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t_DECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF51x processor’s out-
put voltage and the input threshold for the device requiring the
hold time. C_L is the total bus capacitance (per data line), and I_L is
the total leakage or three-state current (per data line). The hold
time is t_DECAY plus the various output disable times as specified
in the Timing Specifications on Page 27 (for example t_DSDAT for
an SDRAM write cycle as shown in SDRAM Interface Timing
on Page 31).
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see Figure 55). V_LOAD is equal
to (V_DDEXT/V_DDMEM)/2. The graphs of Figure 56 through
Figure 67 show how output rise time varies with capacitance.
The delay and hold specifications given should be derated by a
factor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.
V_LOAD
50:
70:
50:
4pF
2pF
400:
TESTER PIN ELECTRONICS
45:
0.5pF
T1
DUT
OUTPUT
ZO = 50: (impedance)
TD = 4.04 ± 1.18 ns
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 55. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
12
10
t_RISE
8
t_FALL
6
4
2
t_RISE = 1.8V @ 25°C
t_FALL = 1.8V @ 25°C
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 56. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V V_DDEXT/V_DDMEM)
Rev. B | Page 53 of 68 | January 2011