ADSP-BF512BBCZ-4F4 Datasheet, PDF (35/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
RSI Controller Timing
Table 31 and Figure 19 describe RSI controller timing. Table 32
and Figure 20 describe RSI controller (high speed) timing.
Table 31. RSI Controller Timing
Parameter
Min
Max
Timing Requirements
t_ISU Input Setup Time
5.6
t_IH
Input Hold Time
2
Switching Characteristics
f_PP1 Clock Frequency Data Transfer Mode
f_OD Clock Frequency Identification Mode
t_WL Clock Low Time
t_WH Clock High Time
t_TLH Clock Rise Time
t_THL Clock Fall Time
t_ODLY Output Delay Time During Data Transfer Mode
t_ODLY Output Delay Time During Identification Mode
0
25
100²
400
10
10
10
10
14
50
1 _{tPP = 1/fPP}
2 _{Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.}
Unit
ns
ns
MHz
kHz
ns
ns
ns
ns
ns
ns
SD_CLK
INPUT
t_PP
t_THL
t_WL
t_TLH
t_WH
t_ISU
t_IH
t_ODLY
OUTPUT
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 19. RSI Controller Timing
V_{OH (MIN)}
V_{OL (MAX)}
Rev. B | Page 35 of 68 | January 2011