AD6655ABCPZ-80 Datasheet, PDF (53/88 Pages) Analog Devices – IF Diversity Receiver

AD6655
Addr.
(Hex)
0x104
0x105
0x106
0x107
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
Register
Name
Fast Detect
Control
(Local)
Coarse Upper
Threshold
(Local)
Fine Upper
Threshold
Register 0
(Local)
Fine Upper
Threshold
Register 1
(Local)
Fine Lower
Threshold
Register 0
(Local)
Fine Lower
Threshold
Register 1
(Local)
Increase Gain
Dwell Time
Register 0
(Local)
Increase Gain
Dwell Time
Register 1
(Local)
Signal
Monitor
DC
Correction
Control
(Global)
Signal
Monitor
DC Value
Channel A
Register 0
(Global)
Signal
Monitor
DC Value
Channel A
Register 1
(Global)
Signal
Monitor
DC Value
Channel B
Register 0
(Global)
Signal
Monitor
DC Value
Channel B
Register 1
(Global)
Signal
Monitor
SPORT
Control
(Global)
Bit 7
(MSB)
Open
Open
Open
Open
Open
Open
Open
Open
Bit 6
Open
Open
Bit 5
Open
Open
Bit 4
Open
Open
Bit 3
Bit 2
Bit 1
Fast Detect Mode Select[2:0]
Bit 0
(LSB)
Fast detect
enable
Default
Value
(Hex)
0x00
Default
Notes/
Comments
Open
Coarse Upper Threshold[2:0]
0x00
Fine Upper Threshold[7:0]
0x00
Open
Open
Fine Upper Threshold[12:8]
0x00
Fine Lower Threshold[7:0]
0x00
Open
Open
Fine Lower Threshold[12:8]
0x00
DC
correction
freeze
Increase Gain Dwell Time[7:0]
Increase Gain Dwell Time[15:8]
DC Correction Bandwidth(k:[3:0])
DC Value Channel A[7:0]
0x00
In ADC clock
cycles
0x00
In ADC clock
cycles
DC
correction
for signal
path
enable
DC
correction
for signal
monitor
enable
0x00
Read only
Open
DC Value Channel A[13:8]
Read only
DC Value Channel B[7:0]
Read only
Open
DC Value Channel B[13:8]
Read only
RMS
magnitude
output
enable
Peak
detector
output
enable
Threshold
crossing
output
enable
SPORT SMI SCLK
divide
00 = Undefined
01 = divide by 2
10 = divide by 4
11 = divide by 8
SPORT
SMI SCLK
sleep
Signal
monitor
SPORT
output
enable
0x04
Rev. A | Page 53 of 88