AD6655ABCPZ-80 Datasheet, PDF (42/88 Pages) Analog Devices – IF Diversity Receiver

AD6655
When the fast detect mode select bits are set to 0b001, 0b010,
or 0b011, a subset of the fast detect output pins are available.
In these modes, the fast detect output pins have a latency of six
clock cycles, and the greater of the two input samples is output
at the DCO rate. Table 23 shows the corresponding ADC input
levels when the fast detect mode select bits are set to 0b001 (that
is, when the ADC fast magnitude is presented on the FD[3:1] pins).
Table 23. ADC Fast Magnitude Nomimal Levels
with Fast Detect Mode Select Bits = 001
ADC Fast
Magitude on
FD[2:0] Pins
Nominal Input
Magnitude
Below FS (dB)
Nominal Input
Magnitude
Uncertainty (dB)
000
<−24
Minimum to −18.07
001
−24 to −14.5
−30.14 to −12.04
010
−14.5 to −10
−18.07 to −8.52
011
−10 to −7
−12.04 to −6.02
100
−7 to −5
−8.52 to −4.08
101
−5 to −3.25
−6.02 to −2.5
110
−3.25 to −1.8
−4.08 to −1.16
111
−1.8 to 0
−2.5 to 0
When the fast detect mode select bits are set to 0b010 or 0b011
(that is, when ADC fast magnitude is presented on the FD[2:1]
pins), the LSB is not provided. The input ranges for this mode
are shown in Table 24.
Table 24. ADC Fast Magnitude Nomimal Levels
with Fast Detect Mode Select Bits = 010 or 011
ADC Fast
Magitude on
FD[2:1] Pins
Nominal Input
Magnitude
Below FS (dB)
Nominal Input
Magnitude
Uncertainty (dB)
00
<−14.5
Minimum to −12.04
01
−14.5 to −7
−18.07 to −6.02
10
−7 to −3.25
−8.52 to −2.5
11
−3.25 to 0
−4.08 to 0
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 12 ADC clock cycles. An overrange at the
input is indicated by this bit 12 clock cycles after it occurs.
GAIN SWITCHING
The AD6655 includes circuitry that is useful in applications
either where large dynamic ranges exist or where gain ranging
converters are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed. Fast detect mode select bits = 010 through fast
detect mode select bits = 101 support various combinations of
the gain switching options.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast
magnitude input level is greater than the level programmed in
the coarse upper threshold register (Address 0x105[2:0]). This
value is compared with the ADC Fast Magnitude Bits[2:0]. The
coarse upper threshold output is output two clock cycles after
the level is exceeded at the input and, therefore, provides a fast
indication of the input signal level. The coarse upper threshold
levels are shown in Table 25. This indicator remains asserted for
a minimum of two ADC clock cycles or until the signal drops
below the threshold level.
Table 25. Coarse Upper Threshold Levels
Coarse Upper Threshold
Register[2:0]
C_UT Is Active When Signal
Magnitude Below FS
Is Greater Than (dB)
000
<−24
001
−24
010
−14.5
011
−10
100
−7
101
−5
110
−3.25
111
−1.8
Fine Upper Threshold (F_UT)
The fine upper threshold indicator is asserted if the input
magnitude exceeds the value programmed in the fine upper
threshold register located in Register 0x106 and Register 0x107.
The 13-bit threshold register is compared with the signal magni-
tude at the output of the ADC. This comparison is subject to
the ADC clock latency but is accurate in terms of converter
resolution. The fine upper threshold magnitude is defined by
the following equation:
dBFS = 20 log(Threshold Magnitude/2¹³)
Fine Lower Threshold (F_LT)
The fine lower threshold indicator is asserted if the input magni-
tude is less than the value programmed in the fine lower threshold
register located at Register 0x108 and Register 0x109. The fine
lower threshold register is a 13-bit register that is compared with
the signal magnitude at the output of the ADC. This comparison
is subject to ADC clock latency but is accurate in terms of
converter resolution. The fine lower threshold magnitude
is defined by the following equation:
dBFS = 20 log(Threshold Magnitude/2¹³)
The operation of the fine upper threshold and fine lower
threshold indicators is shown in Figure 75.
Rev. A | Page 42 of 88