AD6655ABCPZ-80 Datasheet, PDF (32/88 Pages) Analog Devices – IF Diversity Receiver

AD6655
If the internal reference of the AD6655 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 54 depicts
how the internal reference voltage is affected by loading.
0
–0.25
VREF = 0.5V
–0.50
VREF = 1.0V
–0.75
–1.00
–1.25
0
0.5
1.0
1.5
2.0
LOAD CURRENT (mA)
Figure 54. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 55 shows the typical drift characteristics of the
internal reference in both 1.0 V and 0.5 V modes.
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 55. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 18). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6655 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 56) and require no external bias.
CLK+
2pF
AVDD
1.2V
CLK–
2pF
Figure 56. Equivalent Clock Input Circuit
Clock Input Options
The AD6655 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 57 and Figure 58 show two preferred methods for clocking
the AD6655 (at clock rates to up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF transformer. The back-to-back Schottky diodes
across the transformer secondary limit clock excursions into the
AD6655 to approximately 0.8 V p-p differential. This helps prevent
the large voltage swings of the clock from feeding through to other
portions of the AD6655, while preserving the fast rise and fall times
of the signal, which are critical to a low jitter performance.
CLOCK
INPUT
0.1µF
Mini-Circuits^®
ADT1–1WT, 1:1Z
0.1µF
XFMR
50Ω ^100Ω
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLK+
ADC
AD6655
CLK–
Figure 57. Transformer Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
1nF
50Ω
1nF
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2822
CLK+
ADC
AD6655
CLK–
Figure 58. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins as shown in Figure 59. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent
jitter performance.
Rev. A | Page 32 of 88