ADSP-BF522_09 Datasheet, PDF (50/80 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/523/524/525/526/527
Preliminary Technical Data
DATA RECEIVE—INTERNAL CLOCK
DRIVE
EDGE
t_SCLKIW
RSCLKx
t_HOFSI
t_DFSI
t_SFSI
RFSx
SAMPLE
EDGE
t_HFSI
DATA RECEIVE—EXTERNAL CLOCK
DRIVE
EDGE
t_SCLKEW
SAMPLE
EDGE
RSCLKx
t_HOFSE
t_DFSE
t_SFSE
RFSx
t_SDRI
t_{HDR I}
t_SDRE
DRx
DRx
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT—INTERNAL CLOCK
DRIVE
EDGE
t_SCLKIW
SAMPLE
EDGE
TSCLKx
t_HOFSI
t_DFSI
t_SFSI
TFSx
t_HDTI
t_DDTI
DTx
t_HFSI
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE
EDGE
t_SCLKEW
SAMPLE
EDGE
TSCLKx
t_HOFSE
t_DFSE
t_SFSE
TFSx
t_HDTE
t_DDTE
DTx
t_HFSE
t_HDRE
t_HFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 23. Serial Ports
Table 39. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
t_DTENE
t_DDTTE
t_DTENI
t_DDTTI
Data Enable Delay from External TSCLKx¹
Data Disable Delay from External TSCLKx¹
Data Enable Delay from Internal TSCLKx¹
Data Disable Delay from Internal TSCLKx¹
1 _{Referenced to drive edge.}
ADSP-BF522/524/526
V_DDEXT =
1.8 V
V_DDEXT =
2.5/3.3 V
Min Max Min Max
ADSP-BF523/525/527
V_DDEXT =
1.8 V
V_DDEXT =
2.5/3.3 V
Min Max Min Max Unit
0.0
0.0
0.0
0.0
ns
10.0
10.0
t_SCLK+1
t_SCLK+1 ns
–2.0
–2.0
–2.0
–2.0
ns
3.0
3.0
t_SCLK+1
t_SCLK+1 ns
TSCLKx
DTx
DRIVE
DRIVE
t_DTENE/I
t_DDTTE/I
Figure 24. Serial Ports — Enable and Three-State
Rev. PrG | Page 50 of 80 | February 2009