ADSP-BF522_09 Datasheet, PDF (12/80 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF522/523/524/525/526/527
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UARTs are further extended with sup-
port for the infrared data association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
TWI CONTROLLER INTERFACE
The processors include a two wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI is compatible with the widely used
I²C^® bus standard. The TWI module offers the capabilities of
simultaneous master and slave operation, support for both 7-bit
addressing and multimedia data arbitration. The TWI interface
utilizes two pins for transferring clock (SCL) and data (SDA)
and supports the protocol at speeds up to 400k bits/sec. The
TWI interface pins are compatible with 5 V logic levels.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
10/100 ETHERNET MAC
The ADSP-BF526 and ADSP-BF527 processors offer the capa-
bility to directly connect to a network by way of an embedded
Fast Ethernet Media Access Controller (MAC) that supports
both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec)
operation. The 10/100 Ethernet MAC peripheral on the proces-
sor is fully compliant to the IEEE 802.3-2002 standard and it
provides programmable features designed to minimize supervi-
sion, bus use, or message processing by the rest of the processor
system.
Some standard features are:
• Support of MII and RMII protocols for external PHYs.
• Full duplex and half duplex modes.
• Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS.
• Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing.
• Flow control (in full-duplex operation): generation and
detection of PAUSE frames.
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers.
• SCLK operating range down to 25 MHz (active and sleep
operating modes).
• Internal loopback from Tx to Rx.
Some advanced features are:
• Buffered crystal output to external PHY for support of a
single crystal system.
• Automatic checksum computation of IP header and IP
payload fields of Rx frames.
• Independent 32-bit descriptor-driven Rx and Tx DMA
channels.
Preliminary Technical Data
• Frame status delivery to memory via DMA, including
frame completion semaphores, for efficient buffer queue
management in software.
• Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations.
• Convenient frame alignment modes support even 32-bit
alignment of encapsulated Rx or Tx IP packet data in mem-
ory after the 14-byte MAC header.
• Programmable Ethernet event interrupt supports any com-
bination of:
• Any selected Rx or Tx frame status conditions.
• PHY interrupt condition.
• Wakeup frame detected.
• Any selected MAC management counter(s) at half-
full.
• DMA descriptor error.
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value.
• Programmable Rx address filters, including a 64-bin
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames.
• Advanced power management supporting unattended
transfer of Rx and Tx frames and status to/from external
memory via DMA during low-power sleep mode.
• System wakeup from sleep operating mode upon magic
packet or any of four user-definable wakeup frame filters.
• Support for 802.3Q tagged VLAN frames.
• Programmable MDC clock rate and preamble suppression.
• In RMII operation, seven unused pins may be configured
as GPIO pins for other purposes.
PORTS
Because of the rich set of peripherals, the processor groups the
many peripheral signals to four ports—Port F, Port G, Port H,
and Port J. Most of the associated pins are shared by multiple
signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The processor has 48 bidirectional, general-purpose I/O (GPIO)
pins allocated across three separate GPIO modules—PORTFIO,
PORTGIO, and PORTHIO, associated with Port F, Port G, and
Port H, respectively. Port J does not provide GPIO functional-
ity. Each GPIO-capable pin shares functionality with other
processor peripherals via a multiplexing scheme; however, the
GPIO functionality is the default state of the device upon
power-up. Neither GPIO output nor input drivers are active by
Rev. PrG | Page 12 of 80 | February 2009