ADSP-BF522_09 Datasheet, PDF (1/80 Pages) Analog Devices – Blackfin Embedded Processor

Blackfin^® Embedded Processor
Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
FEATURES
Up to 600 MHz high-performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See Operating Conditions for
ADSP-BF523/525/527 on Page 29 and Operating Condi-
tions for ADSP-BF522/524/526 on Page 27
Programmable on-chip voltage regulator
(ADSP-BF523/525/527 processors only)
289-ball (12 mm x 12 mm) and 208-ball (17 mm x 17 mm)
CSP_BGA packages
MEMORY
132K bytes of on-chip memory:
(See Table 1 on Page 3 for L1 and L3 memory size details)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI, and TWI
memory or from host devices including SPI, TWI, and UART
Code Security with Lockbox^TM Secure Technology
One-Time-Programmable (OTP) Memory
Memory management unit providing memory protection
PERIPHERALS
USB 2.0 high speed on-the-go (OTG) with Integrated PHY
IEEE 802.3-compliant 10/100 Ethernet MAC
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Host DMA port (HOSTDP)
Two dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I²S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
Two memory-to-memory DMAs with external request lines
Event handler with 54 interrupt inputs
Serial peripheral interface (SPI) compatible port
Two UARTs with IrDA^® support
Two-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
32-bit up/down counter with rotary support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), with programmable
hysteresis
NAND flash controller (NFC)
Debug/JTAG interface
On-chip PLL capable of 0.5؋to 64؋ frequency multiplication
WATCHDOG TIMER
VOLTAGE REGULATOR*
B
JTAG TEST AND EMULATION
PERIPHERAL
ACCESS BUS
INTERRUPT
CONTROLLER
L1 INSTRUCTION
MEMORY
EAB
16
USB
L1 DATA
MEMORY
DMA
CONTROLLER
DCB
DMA
ACCESS
BUS
DEB
EXTERNAL PORT
FLASH, SDRAM CONTROL
BOOT
ROM
*REGULATOR AVAILABLE ON ADSP-BF523/525/527 PROCESSORS ONLY
OTP MEMORY
RTC
COUNTER
SPORT0
SPORT1
UART1
UART0
NFC
PPI
SPI
TIMER7-1
TIMER0
EMAC
HOST DMA
TWI
GPIO
PORT F
GPIO
PORT G
GPIO
PORT H
PORT J
Figure 1. Processor Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrG
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