ADSP-21462W Datasheet, PDF (50/60 Pages) Analog Devices – SHARC Processor material that is subject to change without notice

ADSP-21462W/ADSP-21465W/ADSP-21467
Preliminary Technical Data
TWI Controller Timing
Table 45 and Figure 37 provide timing information for the TWI
interface. Input Signals (SCL, SDA) are routed to the
DPI_P14–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DPI_P14–1 pins.
Table 45. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices¹
Standard Mode
Parameter
Min
Max
f_SCL
SCL Clock Frequency
TBD
TBD
t_HDSTA
Hold Time (repeated) Start Condition. After This
Period, the First Clock Pulse is Generated.
TBD
t_LOW
Low Period of the SCL Clock
TBD
t_HIGH
High Period of the SCL Clock
TBD
t_SUSTA
Setup Time for a Repeated Start Condition
TBD
t_HDDAT
Data Hold Time for TWI-bus Devices
TBD
t_SUDAT
Data Setup Time
TBD
t_SUSTO
Setup Time for Stop Condition
TBD
t_BUF
Bus Free Time Between a Stop and Start Condition TBD
t_SP
Pulse Width of Spikes Suppressed By the Input Filter n/a
n/a
1 _{All values referred to VIHmin and VILmax levels. For more information, see Electrical Characteristics on page 19.}
Fast Mode
Min
Max
Unit
TBD
TBD
kHz
TBD
μs
μs
TBD
μs
TBD
μs
TBD
μs
TBD
ns
TBD
μs
TBD
μs
TBD
TBD
ns
DPI_P14-1
SDA
t_LOW
t_{SUDA T}
t_{HDS TA}
t _SP
t_{B UF}
DPI_P14-1
SCL
S
t_{HDS TA}
t_{H DDA T}
t_{H IG H}
t_{SUS TA}
Sr
t _SUSTO
P
S
Figure 37. Fast and Standard Mode Timing on the TWI Bus
Rev. PrA | Page 50 of 60 | November 2008