ADSP-21462W Datasheet, PDF (35/60 Pages) Analog Devices – SHARC Processor material that is subject to change without notice

Preliminary Technical Data
Table 29. Link Ports – Transmit
Parameter
Timing Requirements
t_SLACH
LACK Setup Before LCLK High
t_HLACH
LACK Hold After LCLK High
Switching Characteristics
t_DLDCH
t_HLDCH
t_LCLKTWL
t_LCLKTWH
t_DLACLK
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
ADSP-21462W/ADSP-21465W/ADSP-21467
Min
Max
Unit
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
TBD
TBD
ns
t_LCLKTWH
t_LCLKTWL
LAST BYTE
TRANSMITTED
FIRST BYTE
TRANSMITTED
LCLK INACTIVE
(HIGH)
LCLK
t_HLDCH
t_DLDCH
LDAT7-0
OUT
t_SLACH
t_HLACH
LACK (IN)
THE t_SLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST BYTE TRANSMITTED.
t_DLACLK
Figure 21. Link Ports—Transmit
Rev. PrA | Page 35 of 60 | November 2008