ADSP-21161NKCAZ100 Datasheet, PDF (50/60 Pages) Analog Devices – SHARC Processor

ADSP-21161N
SPI Interface Specifications
Table 36. SPI Interface Protocol — Master Switching and Timing
100 MHz
Parameter
Min
Max
Timing Requirements
t_SSPIDM
Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0.5t_CCLK+10
t_HSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid
0.5t_CCLK+1
Switching Characteristics
t_SPICLKM
Serial Clock Cycle
8t_CCLK
t_SPICHM
Serial Clock High Period
4t_CCLK–4
t_SPICLM
Serial Clock Low Period
4t_CCLK–4
t_DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
3
t_HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0
t_{SDSCIM_0}
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for 5t_CCLK
CPHASE = 0
t_{SDSCIM_1}
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for 3t_CCLK
CPHASE = 1
t_HDSM
t_SPITDM
Last SPICLK Edge to FLAG3–0 High
Sequential Transfer Delay
t_CCLK–3
2t_CCLK
110 MHz
Min
Max
0.5t_CCLK+10
0.5t_CCLK+1
8t_CCLK–4
4t_CCLK–4
4t_CCLK–4
3
0
5t_CCLK
3t_CCLK
t_CCLK–3
2t_CCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FLAG3-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
MOSI
(OUTPUT)
CPHASE = 1
MISO
(INPUT)
t_SDSCIM t_SPICHM t_SPICLM
t_SPICLM
t_SPICHM
t_{D DSPIDM}
MSB
t_SSPIDM
MSB
VALID
t_HSPIDM
MOSI
(OUTPUT)
CPHASE = 0
t_SSPIDM
MISO
(INPUT)
MSB
t_HSPIDM
MSB
VALID
t_DDSPIDM
t_SPICLKM
t_HDSM
t_SPITDM
t _HDSPIDM
t_SSPIDM
t_HDSPIDM
LSB
LSB
VALID
t_HSPIDM
LSB
LSB
VALID
Figure 31. SPI Interface Protocol — Master Switching and Timing
Rev. C | Page 50 of 60 | January 2013