ADSP-21161NKCAZ100 Datasheet, PDF (42/60 Pages) Analog Devices – SHARC Processor

ADSP-21161N
SDRAM Interface — Bus Master
Use these specifications for ADSP-21161N bus master accesses
of SDRAM:
Table 26. SDRAM Interface — Bus Master
Parameter
100 MHz
110 MHz
Min
Max
Min
Max
Unit
Timing Requirements
t_SDSDK
Data Setup Before SDCLK
2.0
2.0
ns
t_HDSDK
Data Hold After SDCLK
2.3
2.3
ns
Switching Characteristics
t_DSDK1
t_SDK
t_SDKH
t_SDKL
t_DCADSDK
t_HCADSDK
t_SDTRSDK
t_SDENSDK
t_SDCTR
t_SDCEN
t_SDSDKTR
t_SDSDKEN
t_SDATR
t_SDAEN
First SDCLK Rise Delay After CLKIN^{1, 2}
SDCLK Period
SDCLK Width High
0.75t_CCLK + 1.5
t_CCLK
4
0.75t_CCLK + 8.0
2  t_CCLK
0.75t_CCLK + 1.5
t_CCLK
3
0.75t_CCLK + 8.0 ns
2  t_CCLK
ns
ns
SDCLK Width Low
4
3
ns
Command, Address, Data, Delay After SDCLK³
Command, Address, Data, Hold After SDCLK³ 2.0
0.25t_CCLK +2.5
2.0
0.25t_CCLK +2.5 ns
ns
Data Three-State After SDCLK⁴
Data Enable After SDCLK⁵
Command Three-State After CLKIN
Command Enable After CLKIN
0.75t_CCLK
0.5t_CCLK– 1.5
2
0.5t_CCLK + 2.0
0.5t_CCLK + 6.0
5
0.75t_CCLK
0.5t_CCLK –1.5
2
0.5t_CCLK + 2.0
ns
ns
0.5t_CCLK + 6.0 ns
5
ns
SDCLK Three-State After CLKIN
0
3
0
3
ns
SDCLK Enable After CLKIN
1
4
1
4
ns
Address Three-State After CLKIN
Address Enable After CLKIN
0.25 t_CCLK5
0.25t_CCLK
0.25 t_CCLK5
0.25t_CCLK
ns
0.4
+7.2
0.4
+7.2
ns
1 _{For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the tDSDK1 and tSSDKC1 values, depending upon the SDCKR}
value and the core clock to CLKIN ratio.
2 _{Subtract tCCLK from result if value is greater than or equal to tCCLK.}
3 _{Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE.}
4 _{SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write.}
5 _{Valid when DSP transitions to SDRAM master from SDRAM slave.}
SDRAM Interface — Bus Slave
These timing requirements allow a bus slave to sample the bus
master’s SDRAM command and detect when a refresh occurs:
Table 27. SDRAM Interface — Bus Slave
Parameter
Min
Max
Unit
Timing Requirements
t_SSDKC1
t_SCSDK
t_HCSDK
First SDCLK Rise after CLKOUT^{1, 2, 3}
Command Setup before SDCLK⁴
Command Hold after SDCLK⁴
SDCK  t_CCLK0.5t_CCLK 0.5
2
1
SDCKR  t_CCLK0.25t_CCLK + 2.0
ns
ns
ns
1 _{For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the tDSDK1 and tSSDKC1 values, depending upon the}
SDCKR value and the Core clock to CLKOUT ratio.
2 _{SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency.}
3 _{Subtract tCCLK from result if value is greater than or equal to tCCLK.}
4 _{Command = SDCKE, RAS, CAS, and SDWE.}
Rev. C | Page 42 of 60 | January 2013