ADSP-21161NKCAZ100 Datasheet, PDF (1/60 Pages) Analog Devices – SHARC Processor

SUMMARY
High performance 32-Bit DSP—applications in audio, medi-
cal, military, wireless communications, graphics, imaging,
motor-control, and telephony
Super Harvard Architecture—four independent buses for
dual data fetch, instruction fetch, and nonintrusive zero-
overhead I/O
Code compatible with all other sharc family DSPs
Single-instruction multiple-data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point computation units,
each with a multiplier, ALU, shifter, and register file
Serial ports offer I²S support via 8 programmable and simul-
taneous receive or transmit pins, which support up to 16
transmit or 16 receive channels of audio
SHARC Processor
ADSP-21161N
Integrated peripherals—integrated I/O processor, 1M bit on-
chip dual-ported SRAM, SDRAM controller, glueless multi-
processing features, and I/O ports (serial, link, external
bus, SPI, and JTAG)
ADSP-21161N supports 32-bit fixed, 32-bit float, and 40-bit
floating-point formats
100 MHz/110 MHz core instruction rate
Single-cycle instruction execution, including SIMD opera-
tions in both computational units
Up to 660 MFLOPs peak and 440 MFLOPs sustained
performance
225-ball 17 mm 17 mm CSP_BGA package
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 u 48-BIT
DAG1
8 u 4 u 32
DAG2
8 u 4 u 32
PROGRAM
SEQUENCER
BUS
CONNECT
(PX)
32
PM ADDRESS BUS
32
DM ADDRESS BUS
64
PM DATA BUS
64
DM DATA BUS
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
ADDR
DATA
DATA
ADDR
IOD
IOA
64
18
MULT
DATA
REGISTER
FILE
(PEX)
16 u 40-BIT
BARREL
SHIFTER
BARREL
SHIFTER
DATA
REGISTER
FILE
(PEY)
16 u 40-BIT
MULT
JTAG TEST
6
AND EMULATION
GPIO
12
FLAGS
8
SDRAM
CONTROLLER
EXTERNAL PORT
ADDR BUS
24
MUX
MULTIPROCESSOR
INTERFACE
DATA BUS
32
MUX
HOST PORT
ALU
S
ALU
DMA
5
IOP
CONTROLLER
REGISTERS
(MEMORY MAPPED)
SERIAL PORTS (4)
16
CONTROL,
STATUS, &
DATA BUFFERS
20
LINK PORTS (2)
4
SPI PORTS (1)
I/O PROCESSOR
Figure 1. ADSP-21161N Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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