AD9234 Datasheet, PDF (50/66 Pages) Analog Devices – 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

AD9234
Data Sheet
TEST MODES
ADC TEST MODES
The AD9234 has various test options that aid in the system level
implementation. The AD9234 has ADC test modes that are
available in Register 0x550. These test modes are described in
Table 15. When an output test mode is enabled, the analog section
of the ADC is disconnected from the digital back-end blocks,
and the test pattern is run through the output formatting block.
Some of the test patterns are subject to output formatting, and
some are not. The PN generators from the PN sequence tests
can be reset by setting Bit 4 or Bit 5 of Register 0x550. These
tests can be performed with or without an analog signal (if
present, the analog signal is ignored); however, they do require
an encode clock. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Table 15. ADC Test Modes¹
Output Test Mode
Bit Sequence
Pattern Name
0000
Off (default)
0001
Midscale short
0010
+Full-scale short
0011
−Full-scale short
0100
Checkerboard
0101
PN sequence long
0110
PN sequence short
0111
One-/zero-word toggle
1000
User input
Expression
N/A
0000 0000 0000
0111 1111 1111
1000 0000 0000
1010 1010 1010
X²³ + X¹⁸ + 1
X⁹ + X⁵ + 1
1111 1111 1111
Register 0x551 to
Register 0x558
1111
Ramp output
1 _{N/A means not applicable.}
(X) % 2¹²
Default/
Seed Value
N/A
N/A
N/A
N/A
N/A
0x3AFF
0x0092
N/A
N/A
N/A
Sample (N, N + 1, N + 2,….)
N/A
N/A
N/A
N/A
0x0AAA, 0x0555, 0x0AAA, 0x0555, 0x0AAA
0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6
0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697
0x0FFF, 0x0000, 0x0FFF, 0x0000, 0x0FFF
User Pat 1[15:2], User Pat 2[15:2], User Pat 3[15:2],
User Pat 4[15:2], User Pat 1[15:2] … for repeat mode
User Pat 1[15:2], User Pat 2[15:2], User Pat 3[15:2],
User Pat 4[15:2], 0x0000 … for single mode
(X) % 2¹², (X +1) % 2¹², (X +2) % 2¹², (X +3) % 2¹²
Rev. A | Page 50 of 66