AD9234 Datasheet, PDF (38/66 Pages) Analog Devices – 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

AD9234
Data Sheet
CONVERTER A
INPUT
CONVERTER B
INPUT
CONVERTER 0
ADC
A
MUX/
FORMAT
(SPI
REG 0x561,
REG 0x564)
ADC
B
JESD204B LINK
CONTROL
(L.M.F)
(SPI REG 0x570)
LANE MUX
AND MAPPING
(SPI
REG 0x5B0,
REG 0x5B2,
REG 0x5B3,
REG 0x5B5,
REG 0x5B6)
SERDOUT0–,
SERDOUT0+
SERDOUT1–,
SERDOUT1+
SERDOUT2–,
SERDOUT2+
SERDOUT3–,
SERDOUT3+
CONVERTER 1
SYSREF±
SYNCINB±
Figure 90. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00)
JESD204B
LONG TRANSPORT
TEST PATTERN
REG 0x571[5]
ADC TEST PATTERNS
(RE0x550,
REG 0x551 TO
REG 0x558)
ADC
MSB A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
LSB A0
C2
CONTROL BITS C1
C0
JESD204B SAMPLE
CONSTRUCTION
TAIL BITS
0x571[6]
TRANSPORT
LAYER
JESD204B
INTERFACE
TEST PATTERN
(REG 0x573,
REG 0x551 TO
REG 0x558)
JESD204B DATA
LINK LAYER TEST
PATTERNS
REG 0x574[2:0]
FRAME
CONSTRUCTION
MSB A13 A5
A12 A4
A11 A3
A10 A2
A9 A1
A8 A0
A6 C2
LSB A7 T
SCRAMBLER
1 + x14 + x15
(OPTIONAL)
MSB S7 S7
S6 S6
S5 S5
S4 S4
S3 S3
S2 S2
S1 S1
LSB S0 S0
8-BIT/10-BIT
ENCODER
SERIALIZER
SERDOUT0±
SERDOUT1±
ab
i j ab
ij
abcde f gh i j
abcde f gh i j
SYMBOL0
SYMBOL1
Figure 91. ADC Output Datapath Showing Data Framing
DATA LINK
LAYER
PHYSICAL
LAYER
PROCESSED
SAMPLES
FROM ADC
SAMPLE
FRAME
CONSTRUCTION CONSTRUCTION
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATION
8-BIT/10-BIT
ENCODER
CROSSBAR
MUX
SERIALIZER
Tx
OUTPUT
SYSREF±
SYNCINB±
Figure 92. Data Flow
FUNCTIONAL OVERVIEW
number of tail bits within a sample (JESD204B word):
The block diagram in Figure 92 shows the flow of data through
the JESD204B hardware from the sample input to the physical
output. The processing can be divided into layers that are
derived from the open-source initiative (OSI) model widely
used to describe the abstraction layers of communications
systems. These layers are the transport layer, data link layer,
and physical layer (serializer and output driver).
Transport Layer
The transport layer handles packing the data (consisting of
samples and optional control bits) into JESD204B frames that
are mapped to 8-bit octets. These octets are sent to the data link
layer. The transport layer mapping is controlled by rules derived
from the link parameters. Tail bits are added to fill gaps where
required. The following equation can be used to determine the
T = N΄ – N – CS
Data Link Layer
The data link layer is responsible for the low level functions
of passing data across the link. These include optionally
scrambling the data, inserting control characters for multichip
synchronization/lane alignment/monitoring, and encoding
8-bit octets into 10-bit symbols. The data link layer is also
responsible for sending the initial lane alignment sequence
(ILAS), which contains the link configuration data used by
the receiver to verify the settings in the transport layer.
Physical Layer
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. In this layer, parallel data is converted into
one, two, or four lanes of high speed differential serial data.
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