AD9234 Datasheet, PDF (44/66 Pages) Analog Devices – 12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

AD9234
Data Sheet
Number of Virtual
JESD204B Quick
JESD204B Transport Layer Settings²
Converters Supported Configuration
(Same Value as M)
(0x570)
Serial Line Rate¹ L M F S HD N
N΄ CS
K³
2
0x09
20 × fOUT
1 2 2 1 0 7 to 8 8 0 to 1
0x48
10 × fOUT
2 2 1 1 0 7 to 8 8 0 to 1
0x49
10 × fOUT
2 2 2 2 0 7 to 8 8 0 to 1
0x88
5 × fOUT
4 2 1 2 0 7 to 8 8 0 to 1
0x89
5 × fOUT
4 2 2 4 0 7 to 8 8 0 to 1
0x8A
5 × fOUT
4 2 4 8 0 7 to 8 8 0 to 1
1 _{fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥3125 Mbps and ≤12,500 Mbps; when the serial line rate is}
≤12.5 Gbps and ≥6.25 Gbps, the low line rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial line rate is <6.25 Gbps and ≥3.125 Gbps, the
low line rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E).
2 _{JESD204B transport layer descriptions are as described in the JESD204B Overview section.}
3 _{For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.}
See the Example 1: Full Bandwidth Mode section, the
Example 2: Full Bandwidth Mode at 500 MSPS section, and the
Example 3: ADC with DDC Option (Two ADCs Plus Two
DDCs) section for examples describing which JESD204B
transport layer settings are valid for a given chip mode.
Example 1: Full Bandwidth Mode at 1 GSPS
Chip application mode is full bandwidth mode (see Figure 101).
 Two 12-bit converters at 1000 MSPS
 Full bandwidth application layer mode
 No decimation
JESD204B output configuration includes the following:
 Two virtual converters required (see Table 12)
 Output sample rate (fOUT) = 1000/1 = 1000 MSPS
JESD204B supported output configurations (see Table 12)
include
 N΄ = 16 bits
 N = 12 bits
 L = 4, M = 2, and F = 1, or L = 4, M = 2, and F = 2 (quick
configuration = 0x88 or 0x89)
 CS = 0 to 2
 K = 32
 Output serial line rate = 10 Gbps per lane, low line rate
mode disabled
CMOS
Example 2: Full Bandwidth Mode at 500 MSPS
Chip application mode is full bandwidth mode (see Figure 101).
 Two 12-bit converters at 500 MSPS
 Full bandwidth application layer mode
 No decimation
JESD204B output configuration includes the following:
 Two virtual converters required (see Table 12)
 Output sample rate (fOUT) = 500/1 = 500 MSPS
JESD204B supported output configurations (see Table 12)
include
 N΄ = 16 bits
 N = 12 bits
 L = 4, M = 2, and F = 1, or L = 2, M = 2, and F = 2 (quick
configuration = 0x88 or 0x49)
 CS = 0 to 2
 K = 32
 Output serial line rate
 5 Gbps per lane for L.M.F = 4.2.1, low line rate mode
enabled (0x56E = 0x00)
 10 Gbps per lane for L.M.F = 2.2.2, low line rate mode
disabled (0x56E = 0x00)
REAL/I
REAL/Q
FAST
DETECTION
14-BIT
AT
1Gbps
CONVERTER 0
14-BIT
AT
1Gbps
CONVERTER 1
FAST
DETECTION
JESD204B
TRANSMIT
INTERFACE
L
JESD204B
LANES
AT UP TO
12.5Gbps
CMOS
Figure 101. Full Bandwidth Mode
Rev. A | Page 44 of 66