CN-0243 Datasheet, PDF (5/8 Pages) Analog Devices – High Dynamic Range RF Transmitter Signal Chain Using Single External Frequency Reference for DAC Sample Clock and IQ Modulator LO Generation

Circuit Note
Applying the differential Butterworth filter gives significant
spur level reduction, as shown in Figure 8. The strongest spurs
are still at 2062 MHz, 2242 MHz, and the 2× DAC clock spur at
2400 MHz. All three spurious components have been reduced
significantly.
2098MHz
2062MHz
2242MHz
2400MHz
Figure 8. RF Spectrum Using 5th Order Butterworth Filter, Differential
Capacitors
The common-mode rejection of the DAC/IQ modulator
interface can often be improved by changing the topology of the
interface filter. In Figure 9, the input and output 4.7 pF caps are
replaced by common-mode capacitors (9.0 pF) from both sides
of the filter input and both sides of the filter output to ground.
This does not change the overall differential filter mode
response but does have an effect on this board on the overall
spurious content at RF. The harmonics mentioned earlier at
2098MHz
2062MHz
2242MHz
2400MHz
CN-0243
2062 MHz and 2242 MHz are down a few dB more, and there
has been about a 15 dB reduction in the 2× DAC clock
component, nearly to the noise floor.
The topology and results shown here may vary from layout to
layout, so it is always to the advantage of the designer to
experiment with the layout of the filter, specifically which mix
of differential and common-mode capacitors results in the
lowest overall spur floor.
Synthesizer Path and PLL Phase Noise
As shown in Figure 1, this circuit uses a single external
reference to generate the AD9122 DAC sample clock and the
reference clock for the PLL in the ADRF6702. The AD9516 is
fundamental in providing the flexibility to do this. The AD9516
contains a PLL and integrated VCO. It also contains a number
of outputs that can be programmed for differential LVPECL,
LVDS, or single-ended CMOS, with independent divider
settings for each output path. In this circuit, one of these output
paths is used for the DAC clock and another output is used for
the reference input of the fractional-N PLL in the ADRF6702.
The advantage of using a fractional PLL in the ADRF6702 is
twofold. First, the fractional PLL allows very fine tuning of the
output LO. As an example, with an input frequency of 38.4 MHz
and a programmed MOD value in the ADRF6702 of 1536, the
LO can be programmed in increments of 25 kHz. The second
advantage is that the reference frequency does not have to be
equal to LO freq/divider ratio, but can be much higher, leading
to a lower divider ratio. Because the output phase noise is a
function of the reference phase noise multiplied by the divider
ratio, this means inherently lower phase noise at RF.
One of the key metrics in a synthesizer system is the amount of
phase noise added by the individual PLL and dividers. Figure 10
shows the noise floor of the spectrum analyzer doing the
measurement (green trace), the phase noise of the reference
generator (red), and the phase noise of an output tone at an RF
frequency of 1961 MHz with an LO of 1940 MHz (yellow). The
combination of the PLL in the AD9516 and the ADRF6702 does
generate noticeably high close-in phase noise (less than 500 kHz
offset from carrier) but does not contribute significant
wideband noise to the system. The loop filters for the VCOs in
both the AD9516 and ADRF6702 are set to bandwidths of
~100 kHz in the measurement circuit. Close-in phase noise may
be reduced by lowering the bandwidth of these loop filters.
System specifications should be reviewed to determine how
much close-in phase noise can be tolerated for a given system.
Figure 9. RF Spectrum Using 5th Order Butterworth Filter, Combination of
Differential and Common- Mode Capacitors Used in the DAC_Mod Filter
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