ADSP-2186L_15 Datasheet, PDF (5/36 Pages) Analog Devices – DSP Microcomputer

ADSP-2186L
Pin Terminations (Continued)
Pin
Name
I/O
3-State
(Z)
Reset
State
Hi-Z*
Caused
By
Unused
Configuration
D4 or
IS
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
I/O (Z)
I
I/O (Z)
Hi-Z
I
Hi-Z
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
Hi-Z
Hi-Z
O
O
O
O
O
O
O
I
O
O
I
IRQL1/PF6 I/O (Z) I
IRQL0/PF5 I/O (Z) I
IRQE/PF4 I/O (Z) I
SCLK0
I/O
I
RFS0
I/O
I
DR0
I
I
TFS0
I/O
O
DT0
O
O
SCLK1
I/O
I
RFS1/IRQ0 I/O
I
DR1/FI
I
I
TFS1/IRQ1 I/O
O
DT1/FO
O
O
EE
I
I
EBR
I
I
EBG
O
O
ERESET I
I
EMS
O
O
EINT
I
I
ECLK
I
I
ELIN
I
I
ELOUT
O
O
BR, EBR
BR, EBR
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
EE
Float
High (Inactive)
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
NOTES
*Hi-Z = High Impedance.
1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in Sport0
autobuffer control register.
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.
3. All bidirectional pins have three-stated outputs. When the pin is configured as
an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
Setting Memory Mode
Memory Mode selection for the ADSP-2186L is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are passive and active.
Passive configuration involves the use of a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.
Active configuration involves the use of a three-stateable external
driver connected to the Mode C pin. A driver’s output enable
should be connected to the DSP’s RESET signal such that it
only drives the PF2 pin when RESET is active (low). After
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output.
To minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
Interrupts
The interrupt controller allows the processor to respond to the
thirteen possible interrupts (eleven of which can be enabled
at any one time), and RESET with minimum overhead. The
ADSP-2186L provides four dedicated external interrupt input
pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the PF7:4
pins). In addition, SPORT1 may be reconfigured for IRQ0,
IRQ1, FI and FO, for a total of six external interrupts. The
ADSP-2186L also supports internal interrupts from the timer,
the byte DMA port, the two serial ports, software and the
power-down control circuit. The interrupt levels are internally
prioritized and individually maskable (except power-down and
RESET). The IRQ2, IRQ0 and IRQ1 input pins can be pro-
grammed to be either level- or edge-sensitive. IRQL0 and
IRQL1 are level-sensitive and IRQE is edge-sensitive. The priori-
ties and vector addresses of all interrupts are shown in Table I.
Table I. Interrupt Priority and Interrupt Vector Addresses
Source Of Interrupt
Interrupt Vector Address (Hex)
RESET (or Power-Up with
PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
REV. B
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