ADSP-2186L_15 Datasheet, PDF (4/36 Pages) Analog Devices – DSP Microcomputer

ADSP-2186L
Common-Mode Pins
Pin
Name(s)
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL0/
PF5
IRQL1/
PF6
IRQE/
PF4
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN, XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
FI, FO
PWD
PWDACK
FL0, FL1, FL2
V_DD
GND
V_DD
GND
EZ-Port
# Input/
of Out-
Pins put Function
1I
1I
1O
1O
1O
1O
1O
1O
1O
1O
1O
1I
I/O
1I
I/O
1I
I/O
1I
I/O
1 I/O
1I
I/O
1I
I/O
1I
I/O
2I
1O
5 I/O
5 I/O
1I
1O
3O
6I
10 I
11 I
20 I
9 I/O
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive
Interrupt Request¹
Programmable I/O Pin
Level-Sensitive Interrupt Requests¹
Programmable I/O Pin
Level-Sensitive Interrupt Requests¹
Programmable I/O Pin
Edge-Sensitive Interrupt Requests¹
Programmable I/O Pin
Programmable I/O Pin
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out²
Power-Down Control Input
Power-Down Control Output
Output Flags
Power (LQFP)
Ground (LQFP)
Power (Mini-BGA)
Ground (Mini-BGA)
For Emulation Use³
NOTES
1_{Interrupt/Flag pins retain both functions concurrently. If IMASK is set to}
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.
2_{SPORT configuration determined by the DSP System Control Register. Soft-}
ware configurable.
3_{See Designing an EZ-ICE-Compatible System in this data sheet for complete}
information.
Memory Interface Pins
The ADSP-2186L processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode, which
allows IDMA operation with limited external addressing capabili-
ties. The operating mode is determined by the state of the Mode C
pin during RESET and cannot be changed while the processor is
running. (See Table VI for complete mode operation descriptions.)
Full Memory Mode Pins (Mode C = 0)
#
of
Pin Name Pins
Input/
Output Function
A13:0
D23:0
14 O
24 I/O
Address Output Pins for Pro-
gram, Data, Byte and I/O Spaces
Data I/O Pins for Program,
Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)
Host Mode Pins (Mode C = 1)
#
of
Pin Name Pins
Input/
Output Function
IAD15:0 16 I/O
A0
1
O
D23:8
IWR
IRD
IAL
IS
IACK
16 I/O
1
I
1
I
1
I
1
I
1
O
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data or Byte Access
Data I/O Pins for Program,
Data Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals.
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
Pin
Name
I/O
3-State
(Z)
Reset
State
Hi-Z*
Caused
By
Unused
Configuration
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
D6 or
IRD
D5 or
IAL
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
–4–
REV. B