5962-89481022A Datasheet, PDF (5/8 Pages) Analog Devices – CMOS 12-Bit Monolithic Multiplying DAC

AD7541A
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
Figure 5 and Table III illustrate the circuitry and code relation-
ship for bipolar operation. With a dc reference (positive or nega-
tive polarity) the circuit provides offset binary operation. With
an ac reference the circuit provides full 4-quadrant multiplication.
With the DAC loaded to 1000 0000 0000, adjust R1 for
V_OUT = 0 V (alternatively, one can omit R1 and R2 and adjust
the ratio of R3 to R4 for V_OUT = 0 V). Full-scale trimming can
be accomplished by adjusting the amplitude of V_REF or by vary-
ing the value of R5.
As in unipolar operation, A1 must be chosen for low V_OS and
low I_B. R3, R4 and R5 must be selected for matching and track-
ing. Mismatch of 2R3 to R4 causes both offset and full-scale
error. Mismatch of R5 to R4 or 2R3 causes full-scale error. C1
phase compensation (10 pF to 50 pF) may be required for sta-
bility, depending on amplifier used.
V_DD
R2*
16
18
C1
33pF
R4
20kΩ
V_DD
R_FB
OUT1 1
V_IN
R1* ^{17 VREF AD7541A}
OUT2 2
PINS 4–15
GND
3
A1
AD544L
R3
10kΩ
R6
5kΩ
10%
R5
20kΩ
A2
AD544J
V_OUT
BIT 1 – BIT 12
DIGITAL
GROUND
ANALOG
COMMON
*FOR VALUES OF R1 AND R2
SEE TABLE 1.
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
Table III. Bipolar Code Table for Offset Binary Circuit of
Figure 5
Binary Number in DAC
MSB
LSB
Analog Output, V_OUT
1111 1111 1111
1000 0000
1000 0000
0111 1111
0001
0000
1111
0000 0000 0000
 2047 
+V_{IN  2048 }
 1
+V_{IN  2048 }
0 Volts
 1
–V_{IN  2048 }
 2048 
–V_{IN  2048 }
Figure 6 and Table IV show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage of giving 12-bit resolution in each
quadrant, compared with 11-bit resolution per quadrant for the
circuit of Figure 5. The AD7592 is a fully protected CMOS
changeover switch with data latches. R4 and R5 should match
each other to 0.01% to maintain the accuracy of the D/A con-
verter. Mismatch between R4 and R5 introduces a gain error.
V_DD
R2*
16
18
C1
33pF
V_DD
R_{FB OUT1 1}
V_IN
R1* ^{17 VREF AD7541A}
OUT2 2
PINS 4–15
GND
3
A1
AD544L
SIGN BIT
DIGITAL
GROUND
ANALOG
COMMON
R4
20kΩ
R5
20kΩ
R3
10kΩ
10%
V_OUT
A2
AD544J
1/2 AD7592JN
BIT 1 – BIT 12
*FOR VALUES OF R1 AND R2
SEE TABLE 1.
Figure 6. 12-Bit Plus Sign Magnitude Operation
Table IV. 12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 6
Sign Binary Number in DAC
Bit MSB
LSB
Analog Output, V_OUT
0
1111 1111 1111
0
0000 0000 0000
1
0000 0000 0000
1
1111 1111 1111
Note: Sign bit of “0” connects R3 to GND.
 4095 
+V_IN × _{ 4096 }
0 Volts
0 Volts
 4095 
–V_IN × _{ 4096 }
REV. B
–5–