5962-89481022A Datasheet, PDF (4/8 Pages) Analog Devices – CMOS 12-Bit Monolithic Multiplying DAC

AD7541A
GENERAL CIRCUIT INFORMATION
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used—that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.
V_REF
10kΩ
10kΩ
10kΩ
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
S1
S2
S3
S12
10kΩ
BIT 1 (MSB) BIT 2
BIT 3
BIT 12 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
LOGIC: A SWITCH IS CLOSED TO I_OUT1 FOR
ITS DIGITAL INPUT IN A "HIGH" STATE.
OUT2
OUT1
R_FEEDBACK
Figure 1. Functional Diagram (Inputs HIGH)
The input resistance at V_REF (Figure 1) is always equal to R_LDR
(R_LDR is the R/2R ladder characteristic resistance and is equal to
value “R”). Since R_IN at the V_REF pin is constant, the reference
terminal can be driven by a reference voltage or a reference
current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external R_FB is
recommended to define scale factor.)
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs LOW and all digital
inputs HIGH are shown in Figures 2 and 3. In Figure 2 with all
digital inputs LOW, the reference current is switched to OUT2.
The current source I_LEAKAGE is composed of surface and junc-
tion leakages to the substrate, while the I/₄₀₉₆ current source
represents a constant 1-bit current drain through the termina-
tion resistor on the R-2R ladder. The ON capacitance of the
output N-channel switch is 200 pF, as shown on the OUT2
terminal. The OFF switch capacitance is 70 pF, as shown on
the OUT1 terminal. Analysis of the circuit for all digital inputs
HIGH, as shown in Figure 3 is similar to Figure 2; however, the
ON switches are now on terminal OUT1, hence the 200 pF at
that terminal.
RFB
R
I_LEAKAGE
70pF
OUT1
V_REF
R 15kΩ
I_REF
I_/4096
I_LEAKAGE
200pF
OUT2
Figure 2. DAC Equivalent Circuit All Digital Inputs LOW
V_REF
R 15kΩ
I_REF
I_/4096
I_LEAKAGE
R
200pF
I_LEAKAGE
70pF
RFB
OUT1
OUT2
Figure 3. DAC Equivalent Circuit All Digital Inputs HIGH
APPLICATIONS
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at Pin 17, the circuit is a unipolar D/A converter. With an
ac reference voltage or current, the circuit provides 2-quadrant
multiplication (digitally controlled attenuation). The input/
output relationship is shown in Table II.
R1 provides full-scale trim capability [i.e., load the DAC register
to 1111 1111 1111, adjust R1 for V_OUT = –V_REF (4095/4096)].
Alternatively, Full Scale can be adjusted by omitting R1 and R2
and trimming the reference voltage magnitude.
C1 phase compensation (10 pF to 25 pF) may be required for
stability when using high speed amplifiers. (C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT1).
Amplifier A1 should be selected or trimmed to provide V_OS ≤
10% of the voltage resolution at V_OUT. Additionally, the ampli-
fier should exhibit a bias current which is low over the tempera-
ture range of interest (bias current causes output offset at V_OUT
equal to I_B times the DAC feedback resistance, nominally 11 kΩ).
The AD544L is a high speed implanted FET input op amp with
low factory-trimmed V_OS.
V_DD
R2*
16
18
V_IN
V_DD
R_FB
OUT1 1
R1* ^{17 VREF AD7541A}
OUT2 2
PINS 4–15
DGND
3
C1
33pF
V_OUT
AD544L
(SEE TEXT)
BIT 1 – BIT 12
DIGITAL
GROUND
ANALOG
COMMON
*REFER TO TABLE 1
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades
Trim
Resistor
R1
R2
JN/AQ/SD KN/BQ/TD
100 Ω
47 Ω
100 Ω
33 Ω
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC
MSB
LSB
Analog Output, V_OUT
1111 1111 1111
1000 0000 0000
0000 0000
0000 0000
0001
0000
 4095 
–V_{IN  4096 }
 2048 
–V_{IN  4096 } = –1/2 V_IN
 1
–V_{IN  4096 }
0 Volts
–4–
REV. B