ADSP-BF548_15 Datasheet, PDF (49/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
DDR SDRAM/Mobile DDR SDRAM Timing
Table 32 and Figure 18/Figure 19 describe DDR
SDRAM/mobile DDR SDRAM read cycle timing.
Table 32. DDR SDRAM/Mobile DDR SDRAM Read Cycle Timing
Parameter
Timing Requirements
t_AC
t_DQSCK
t_DQSQ
Access Window of DQ0-15 to DCK0-1
Access Window of DQS0-1 to DCK0-1
DQS0-1 to DQ0-15 Skew, DQS0-1 to Last
DQ0-15 Valid
t_QH
DQ0-15 to DQS0-1 Hold, DQS0-1 to First
DQ0-15 to Go Invalid
t_RPRE
DQS0-1 Read Preamble
t_RPST
DQS0-1 Read Postamble
1 _{For 7.50 ns  tCK < 10 ns.}
2 _{For tCK  10 ns.}
DDR SDRAM
Min
–1.25
–1.25
t_CK/2 – 1.25¹
t_CK/2 – 1.75²
0.9
0.4
Max
+1.25
+1.25
0.90
1.1
0.6
Mobile DDR SDRAM
Min
Max
0.0
6.00
0.0
6.00
0.85
t_CK/2 – 1.25
0.9
1.1
0.4
0.6
Unit
ns
ns
ns
ns
t_CK
t_CK
DCK0-1
DQS0-1
t_DQSCK
t_AC
t_RPRE
t_RPST
DQ0-15
t_DQSQ
Dn
Dn+1
Dn+2
Dn+3
t_QH
Figure 18. DDR SDRAM Controller Read Cycle Timing
DCK0-1
DQS0-1
t_DQSCK
t_AC
t_RPRE
t_RPST
DQ0-15
Dn
Dn+1
Dn+2
Dn+3
t_DQSQ
t_QH
Figure 19. Mobile DDR SDRAM Controller Read Cycle Timing
Rev. E | Page 49 of 102 | March 2014