ADSP-BF548_15 Datasheet, PDF (20/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
For large page NAND flash devices, the 4-byte electronic
signature is read in order to configure the kernel for boot-
ing. This allows support for multiple large page devices.
The fourth byte of the electronic signature must comply
with the specifications in Table 9.
Any configuration from Table 9 that also complies with the
command set listed below is directly supported by the boot
kernel. There are no restrictions on the page size or block
size as imposed by the small-page boot kernel.
Table 9. Byte 4 Electronic Signature Specification
Page Size (excluding D1:D0 00
spare area)
01
10
11
Spare Area Size D2
0
1
Block Size (excluding D5:4 00
spare area)
01
10
11
Bus Width
D6
0
1
Not Used for
Configuration
D3, D7
1K bytes
2K bytes
4K bytes
8K bytes
8 bytes/512 bytes
16 bytes/512 bytes
64K bytes
128K bytes
256K bytes
512K bytes
x8
x16
Large page devices must support the following command set:
Reset: 0xFF
Read Electronic Signature: 0x90
Read: 0x00, 0x30 (confirm command)
Large page devices must not support or react to NAND flash
command 0x50. This is a small page NAND flash command
used for device auto detection.
By default, the boot kernel will always issue five address cycles;
therefore, if a large page device requires only four cycles, the
device must be capable of ignoring the additional address cycle.
16-bit NAND flash memory devices must only support the issu-
ing of command and address cycles via the lower eight bits of
the data bus. Devices that use the full 16-bit bus for command
and address cycles are not supported.
• Boot from OTP memory (BMODE = 0xB)—This provides
a standalone booting method. The boot stream is loaded
from on-chip OTP memory. By default, the boot stream is
expected to start from OTP page 0x40 and can occupy all
public OTP memory up to page 0xDF (2560 bytes). Since
the start page is programmable, the maximum size of the
boot stream can be extended to 3072 bytes.
• Boot from 16-bit host DMA (BMODE = 0xE)—In this
mode, the host DMA port is configured in 16-bit acknowl-
edge mode with little endian data format. Unlike other
modes, the host is responsible for interpreting the boot
stream. It writes data blocks individually into the host
DMA port. Before configuring the DMA settings for each
block, the host may either poll the ALLOW_CONFIG bit in
HOST_STATUS or wait to be interrupted by the HWAIT
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to con-
figure the host DMA port. After completing the
configuration, the host is required to poll the READY bit in
HOST_STATUS before beginning to transfer data. When
the host sends an HIRQ control command, the boot kernel
issues a CALL instruction to address 0xFFA0 0000. It is the
host’s responsibility to ensure valid code has been placed at
this address. The routine at address 0xFFA0 0000 can be a
simple initialization routine to configure internal
resources, such as the SDRAM controller, which then
returns using an RTS instruction. The routine may also be
the final application, which will never return to the boot
kernel.
• Boot from 8-bit host DMA (BMODE = 0xF)—In this
mode, the host DMA port is configured in 8-bit interrupt
mode with little endian data format. Unlike other modes,
the host is responsible for interpreting the boot stream. It
writes data blocks individually to the host DMA port.
Before configuring the DMA settings for each block, the
host may either poll the ALLOW_CONFIG bit in
HOST_STATUS or wait to be interrupted by the HWAIT
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to con-
figure the host DMA port. The host will receive an
interrupt from the HOST_ACK signal every time it is
allowed to send the next FIFO depth’s worth (sixteen 32-bit
words) of information. When the host sends an HIRQ con-
trol command, the boot kernel issues a CALL instruction to
address 0xFFA0 0000. It is the host's responsibility to
ensure valid code has been placed at this address. The rou-
tine at address 0xFFA0 0000 can be a simple initialization
routine to configure internal resources, such as the
SDRAM controller, which then returns using an RTS
instruction. The routine may also be the final application,
which will never return to the boot kernel.
For each of the boot modes, a 16-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
Prior to booting, the pre-boot routine interrogates the OTP
memory. Individual boot modes can be customized or disabled
based on OTP programming. External hardware, especially
booting hosts, may monitor the HWAIT signal to determine
Rev. E | Page 20 of 102 | March 2014