ADSP-BF548_15 Datasheet, PDF (44/102 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Asynchronous Memory Read Cycle Timing
Table 27 and Table 28 on Page 45 and Figure 13 and Figure 14
on Page 45 describe asynchronous memory read cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 27. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Timing Requirements
t_SDAT
DATA15–0 Setup Before CLKOUT
t_HDAT
DATA15–0 Hold After CLKOUT
t_SARDY
ARDY Setup Before the Falling Edge of CLKOUT
t_HARDY
ARDY Hold After the Falling Edge of CLKOUT
Switching Characteristics
t_DO
Output Delay After CLKOUT¹
t_HO
Output Hold After CLKOUT¹
1 _{Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE.}
Min
Max
Unit
5.0
ns
0.8
ns
5.0
ns
0.0
ns
6.0
ns
0.3
ns
CLKOUT
AMSx
SETUP
2 CYCLES
t_DO
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
HOLD
3 CYCLES
1 CYCLE
t_HO
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
t_DO
t_SARDY
t_HO
t_HARDY
t_HARDY
t_SARDY
t_SDAT
t_HDAT
Figure 13. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Rev. E | Page 44 of 102 | March 2014