AD9979_15 Datasheet, PDF (46/56 Pages) Analog Devices – 14-Bit, CCD Signal Processor with Precision Timing Core

AD9979
Table 29. Timing Core Registers
Data Bit Default Update
Address Content Value Type
30
[5:0]
0
SCK
[7:6]
[13:8] 20
[15:14] 0
[16]
1
[27:17]
31
[5:0]
0
SCK
[7:6]
[13:8] 20
[15:14] 0
[16]
1
[27:17]
32
[5:0]
0
SCK
[7:6]
[13:8] 20
[15:14] 0
[16]
1
[27:17]
33
[5:0]
0
SCK
[7:6]
[13:8] 10
[15:14] 0
[16]
1
[27:17]
34
[0]
0
SCK
[1]
0
[2]
0
[3]
0
[7:4]
0
[27:8]
Name
H1POSLOC
Unused
H1NEGLOC
TESTMODE
H1POL
Unused
H2POSLOC
Unused
H2NEGLOC
TESTMODE
H2POL
Unused
HLPOSLOC
Unused
HLNEGLOC
TESTMODE
HLPOL
Unused
RGPOSLOC
Unused
RGNEGLOC
TESTMODE
RGPOL
Unused
H1BLKRETIME
H2BLKRETIME
HLBLKRETIME
HL_HBLK_EN
HCLK_WIDTH
Unused
Description
H1 rising edge location.
Set unused bits to 0.
H1 falling edge location.
Test operation only. Set to 0.
H1 polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
H2 rising edge location.
Set unused bits to 0.
H2 falling edge location.
Test operation only. Set to 0.
H2 polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
HL rising edge location.
Set unused bits to 0.
HL falling edge location.
Test operation only. Set to 0.
HL polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
RG rising edge location.
Set unused bits to 0.
RG falling edge location.
Test operation only. Set to 0.
RG polarity control.
0 = inverse of Figure 19.
1 = no inversion.
Set unused bits to 0.
Retime H1 HBLK to internal clock.¹
0 = no retime.
1 = enable retime.
Retime H2 HBLK to internal clock.^{1, 2}
Retime HL HBLK to internal clock.^{1, 2}
Enables HBLK for HL output.
0 = disable.
1 = enable.
Enables wide horizontal clocks during HBLK interval.
0 = disable (see Table 12).
Set unused bits to 0.
Rev. C | Page 46 of 56