AD9979_15 Datasheet, PDF (42/56 Pages) Analog Devices – 14-Bit, CCD Signal Processor with Precision Timing Core

AD9979
UPDATING OF NEW REGISTER VALUES
The internal registers of the AD9979 are updated at different
times, depending on the register. Table 23 summarizes the three
different types of register updates. The register listing tables also
contain a column with update type to identify when each register is
updated (see Table 24 to Table 34).
SCK Updated (SCK)
Some of the registers are updated immediately, as soon as the
28th data bit (D27) is written. These registers are used for
functions that do not require gating with the next VD boundary,
such as power-up and reset functions.
VD Updated (VD)
Many of the registers are updated at the next VD falling edge.
By updating these values at the next VD edge, the current field
is not corrupted and the new register values are applied to the
next field. The VD update can be further delayed past the VD
falling edge, using UPDATE (Address 0x17, Bits[12:0]), which
delays the VD-updated register updates to any HD line in the
field. Note that the field registers are not affected by UPDATE.
SCP Updated (SCP)
All of the H-pattern group registers are updated at the next SCP
in which the registers are used.
Table 23. Register Update Locations
Update Type Description
SCK
Register is immediately updated when the 28th data bit (D27) is clocked in.
VD
Register is updated at the VD falling edge. VD-updated registers can be delayed further, using UPDATE (Address 0x17,
Bits[12:0]). Field registers are not affected by UPDATE.
SCP
Register is updated at the next SCP in which the register is used.
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