AD9516-3_15 Datasheet, PDF (45/80 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.0 GHz VCO

Data Sheet
Table 44. Divider 3, Divider 4 Duty Cycle; VCO Divider Not
Used; Duty Cycle Correction On (DCCOFF = 0)
Input
Clock
Duty
Cycle
DX.1
NX.1 + MX.1 + 2
DX.2
NX.2 + MX.2 + 2
Output
Duty Cycle
50% 1
1
50%
50% Even
1
(NX.1 = MX.1)
50%
X% 1
1
X% (High)
X% Even
1
(NX.1 = MX.1)
50%
50%
Odd
1
(MX.1 = NX.1 + 1)
50%
X% Odd
1
(MX.1 = NX.1 + 1)
(NX.1 + 1 + X%)/
(2NX.1 + 3)
Odd
1
(MX.1 = NX.1 + 1)
(NX.1 + 1 + X%)/
(2NX.1 + 3)
50%
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
X% Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
50%
Odd
Even
(MX.1 = NX.1 + 1) (NX.2 = MX.2)
50%
X% Odd
Even
(MX.1 = NX.1 + 1) (NX.2 = MX.2)
50%
50%
Odd
Odd
50%
(MX.1 = NX.1 + 1) (MX.2 = NX.2 + 1)
X% Odd
Odd
(2NX.1NX.2 + 3NX.1 +
(MX.1 = NX.1 + 1) (MX.2 = NX.2 + 1) 3NX.2 + 4 + X%)/
((2NX.1 + 3)(2NX.2 + 3))
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
Divider 3 and Divider 4 can be set to have a phase offset or
delay. The phase offset is set by a combination of the bits in the
phase offset and start high registers (see Table 45).
Table 45. Setting Phase Offset and Division for Divider 3 and
Divider 4
Start
Phase
Low
Divider High (SH) Offset (PO) Cycles M
High
Cycles N
3 3.1 0x19C[0] 0x19A[3:0] 0x199[7:4] 0x199[3:0]
3.2 0x19C[1] 0x19A[7:4] 0x19B[7:4] 0x19B[3:0]
4 4.1 0x1A1[0] 0x19F[3:0] 0x19E[7:4] 0x19E[3:0]
4.2 0x1A1[1] 0x19F[7:4] 0x1A0[7:4] 0x1A0[3:0]
AD9516-3
Let Δt = delay (in seconds).
Φx.y = 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +
1 × PO[0].
TX.1 = period of the clock signal at the input to DX.1 (in seconds).
TX.2 = period of the clock signal at the input to DX.2 (in seconds).
Case 1
When Φx.1 ≤ 15 and Φx.2 ≤ 15:
Δt = Φx.1 × TX.1 + ΦX.2 × Tx.2
Case 2
When Φx.1 ≤ 15 and Φx.2 ≥ 16:
Δt = ΦX.1 × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2
Case 3
When ΦX.1 ≥ 16 and ΦX.2 ≤ 15:
Δt = (ΦX.1 − 16 + MX.1 + 1) × TX.1 + ΦX.2 × TX.2
Case 4
When ΦX.1 ≥ 16 and ΦX.2 ≥ 16:
Δt =
(ΦX.1 − 16 + MX.1 + 1) × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2
Fine Delay Adjust (Divider 3 and Divider 4)
Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes
an analog delay element that can be programmed to give
variable time delays (Δt) in the clock signal at that output.
VCO
CLK DIVIDER
DIVIDER
X.1
DIVIDER
X.2
BYPASS
Δt
FINE DELAY
ADJUST
CMOS
LVDS
CMOS
BYPASS
Δt
FINE DELAY
ADJUST
CMOS
LVDS
CMOS
OUTM
OUTM
OUTPUT
DRIVERS
OUTN
OUTN
Figure 56. Fine Delay (OUT6 to OUT9)
The amount of delay applied to the clock signal is determined
by programming four registers per output (see Table 46).
Table 46. Setting Analog Fine Delays
OUTPUT
Ramp
Ramp
(LVDS/CMOS) Capacitors Current
OUT6
0x0A1[5:3] 0x0A1[2:0]
OUT7
0x0A4[5:3] 0x0A4[2:0]
OUT8
0x0A7[5:3] 0x0A7[2:0]
OUT9
0x0AA[5:3] 0x0AA[2:0]
Delay
Fraction
0x0A2[5:0]
0x0A5[5:0]
0x0A8[5:0]
0x0AB[5:0]
Delay
Bypass
0x0A0[0]
0x0A3[0]
0x0A6[0]
0x0A9[0]
Rev. C | Page 45 of 80