AD9516-3_15 Datasheet, PDF (39/80 Pages) Analog Devices – 14-Output Clock Generator with Integrated 2.0 GHz VCO

Data Sheet
AD9516-3
REF_SEL
VS GND
RSET
REFMON
CPRSET VCP
REFIN (REF1)
REF1
REF2
REFERENCE
SWITCHOVER
STATUS
STATUS
DISTRIBUTION
REFERENCE
R
DIVIDER
PROGRAMMABLE
R DELAY
LOCK
DETECT
LD
HOLD
REFIN (REF2)
BYPASS
LOW DROPOUT
REGULATOR (LDO)
N DIVIDER
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
LF
CLK
CLK
VCO
DIVIDE BY
2, 3, 4, 5, OR 6
VCO STATUS
0
1
STATUS
10
Figure 54. Reference and VCO Status Monitors
VCO Calibration
The AD9516 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off of a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be present.
During the first initialization after a power-up or a reset of the
AD9516, a VCO calibration sequence is initiated by setting
Register 0x018[0] = 1b. This can be done as part of the initial
setup, before executing update registers (Register 0x232[0] = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting Register 0x018[0] = 0b, executing an update
registers operation, setting Register 0x018[0] = 1b, and executing
another update registers operation. A readback bit, Bit 6 in
Register 0x01F, indicates when a VCO calibration is finished
by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is as follows:
 Program the PLL registers to the proper values for the
PLL loop. Note that that automatic holdover mode
must be disabled, and the VCO divider must not be
set to “Static.”
 Ensure that the input reference signal is present.
 For the initial setting of the registers after a power-up or
reset, initiate VCO calibration by setting Register
0x018[0] = 1b. Subsequently, whenever a calibration is
desired, set Register 0x018[0] = 0b, update registers;
and then set Register 0x018[0] = 1b, update registers.
 A SYNC operation is initiated internally, causing the
outputs to go to a static state determined by normal
SYNC function operation.
 VCO calibrates to the desired setting for the requested
VCO frequency.
 Internally, the SYNC signal is released, allowing
outputs to continue clocking.
 PLL loop is closed.
A sync is executed during the VCO calibration; therefore, the
outputs of the AD9516 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 54
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
Table 29. Example Time to Complete a VCO Calibration
with Different fREFIN Frequencies
fREFIN (MHz) R Divider PFD
Time to Calibrate VCO
100
1
100 MHz 88 μs
10
10
1 MHz 8.8 ms
10
100
100 kHz 88 ms
 PLL locks.
Rev. C | Page 39 of 80