ADSP-BF514KBCZ-3 Datasheet, PDF (44/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Timer Cycle Timing
Table 41 and Figure 29 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f_SCLK/2) MHz.
Table 41. Timer Cycle Timing
V_DDEXT
1.8V Nominal
V_DDEXT
2.5 V/3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Characteristics
t_WL1
Timer Pulse Width Input Low (Measured In SCLK Cycles) t_SCLK
t_SCLK
ns
t_WH1
Timer Pulse Width Input High (Measured In SCLK Cycles) t_SCLK
t_SCLK
ns
t_TIS2
Timer Input Setup Time Before CLKOUT Low
10
7
ns
t_TIH2
Timer Input Hold Time After CLKOUT Low
–2
–2
ns
Switching Characteristics
t_HTO
Timer Pulse Width Output (Measured In SCLK Cycles)
t_SCLK – 1.5
(2³²â€“1)t_SCLK t_SCLK – 1
(2³²â€“1)t_SCLK ns
t_TOD
Timer Output Update Delay After CLKOUT High
6
6
ns
1 _{The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.}
2 _{Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.}
CLKOUT
TMRx OUTPUT
TMRx INPUT
t_TOD
t_TIS
t_TIH
t_HTO
t_WH,t_WL
Figure 29. Timer Cycle Timing
Rev. B | Page 44 of 68 | January 2011