ADSP-BF514KBCZ-3 Datasheet, PDF (2/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
Revision History ...................................................... 2
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 5
Event Handling .................................................... 6
DMA Controllers .................................................. 7
Processor Peripherals ............................................. 7
Dynamic Power Management ................................ 11
Voltage Regulation Interface .................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 15
Development Tools ............................................. 15
Designing an Emulator-Compatible
Processor Board (Target) ................................... 16
Related Documents ............................................. 16
Related Signal Chains ........................................... 16
Lockbox Secure Technology Disclaimer .................... 16
Signal Descriptions ................................................. 17
Specifications ........................................................ 20
Operating Conditions ........................................... 20
Electrical Characteristics ....................................... 22
Flash Memory Characteristics ................................ 24
Absolute Maximum Ratings ................................... 25
Package Information ............................................ 26
ESD Sensitivity ................................................... 26
Timing Specifications ........................................... 27
Output Drive Currents ......................................... 50
Test Conditions .................................................. 52
Thermal Characteristics ........................................ 56
176-Lead LQFP Lead Assignment ............................... 57
168-Ball CSP_BGA Ball Assignment ........................... 60
Outline Dimensions ................................................ 63
Surface-Mount Design .......................................... 64
Automotive Products .............................................. 65
Ordering Guide ..................................................... 65
REVISION HISTORY
1/11—Rev. A to Rev. B
This data sheet release coincides with the release of the revised
ADSP-BF51x Blackfin Processor Hardware Reference. All
redundant information has been removed.
Revised several specifications in Operating Conditions ... 20
Revised f_VCO specification in Phase-Locked Loop Operating
Conditions ........................................................... 21
Revised several specifications in Electrical Characteristics 22
Added additional f_CKIN specification for automotive models in
Clock and Reset Timing .......................................... 27
Changed the parameter V_DDMEM to V_DDEXT in Asynchronous
Memory Read Cycle Timing ..................................... 29
SDRAM Interface Timing ........................................ 31
Parallel Peripheral Interface Timing ........................... 33
Serial Ports ........................................................... 37
Revised t_HFSPE specification in Parallel Peripheral Interface Tim-
ing ..................................................................... 33
Revised t_HFSPE specification and added the t_PSUD specification in
Parallel Peripheral Interface Timing ........................... 33
Revised the t_WL and t_WH specifications in
RSI Controller Timing ............................................ 35
Revised t_WL, t_WH and t_OH specification in RSI Controller Timing
(High Speed Mode) ................................................. 36
Revised t_MDCIH and t_MDCOH specifications in 10/100 Ethernet
MAC Controller Timing: MII Station Management ........ 48
Corrected dimensions in 168-Ball Chip Scale Package Ball Grid
Array [CSP_BGA] (BC-168-1) ................................... 64
Rev. B | Page 2 of 68 | January 2011