ADSP-BF514KBCZ-3 Datasheet, PDF (29/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Asynchronous Memory Read Cycle Timing
Table 26. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
t_SDAT
DATA15–0 Setup Before CLKOUT
t_HDAT
DATA15–0 Hold After CLKOUT
t_SARDY
ARDY Setup Before CLKOUT
t_HARDY
ARDY Hold After CLKOUT
Switching Characteristics
t_DO
Output Delay After CLKOUT¹
t_HO
Output Hold After CLKOUT ¹
1 _{Output pins/balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.}
V_DDMEM
1.8V Nominal
Min
Max
2.1
1.2
4
0.2
6
0.8
V_DDMEM
2.5 V/3.3V Nominal
Min
Max
Unit
2.1
ns
0.8
ns
4
ns
0.2
ns
6
ns
0.8
ns
CLKOUT
AMSx
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
SETUP
2 CYCLES
t_DO
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
HOLD
3 CYCLES
1 CYCLE
t_HO
t_DO
t_SARDY
t_HO
t_HARDY
t_SARDY
t_HARDY
t_SDAT
t_HDAT
Figure 10. Asynchronous Memory Read Cycle Timing
Rev. B | Page 29 of 68 | January 2011