ADSP-21369KSWZ-2A Datasheet, PDF (44/60 Pages) Analog Devices – SHARC Processors

ADSP-21367/ADSP-21368/ADSP-21369
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 39. S/PDIF Receiver Internal Digital PLL Mode Timing
Parameter
Min
Switching Characteristics
t_DFSI
LRCLK Delay After SCLK
t_HOFSI
LRCLK Hold After SCLK
–2
t_DDTI
Transmit Data Delay After SCLK
t_HDTI
Transmit Data Hold After SCLK
–2
t1
SCLKIW
Transmit SCLK Width
40
1 _{SCLK frequency is 64 × FS where FS = the frequency of LRCLK.}
Max
Unit
5
ns
ns
5
ns
ns
ns
DRIVE EDGE
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL
A/B)
t_DFSI
t_HOFSI
t_DDTI
t_HDTI
t_SCLKIW
SAMPLE EDGE
Figure 34. S/PDIF Receiver Internal Digital PLL Mode Timing
Rev. E | Page 44 of 60 | July 2009