ADSP-21369KSWZ-2A Datasheet, PDF (4/60 Pages) Analog Devices – SHARC Processors

ADSP-21367/ADSP-21368/ADSP-21369
The block diagram of the ADSP-21368 on Page 1 also shows the
peripheral clock domain (also known as the I/O processor) and
contains the following features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an AMI and SDRAM controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision
clock generators (PCG), a input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes three timers, a 2-
wire interface, two UARTs, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG) and a flexible sig-
nal routing unit (DPI SRU).
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-
ble at the assembly level with the ADSP-2126x, ADSP-21160,
and ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-21367/ADSP-21368/
ADSP-21369 processors share architectural features with the
ADSP-2126x and ADSP-2116x SIMD SHARC processors, as
shown in Figure 2 and detailed in the following sections.
S
SIMD Core
DMD/PMD 64
DAG1
16x32
DAG2
16x32
JTAG FLAG TIMER INTERRUPT CACHE
5 STAGE
PROGRAM SEQUENCER
PM DATA 48
PM ADDRESS 24
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
DM DATA 64
SYSTEM
I/F
USTAT
4x32-BIT
PX
64-BIT
MULTIPLIER SHIFTER ALU
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ALU
SHIFTER MULTIPLIER
MRF
80-BIT
MRB
80-BIT
ASTATx
STYKx
ASTATy
STYKy
MSB
80-BIT
MSF
80-BIT
Figure 2. SHARC Core Block Diadram
Rev. E | Page 4 of 60 | July 2009