ADSP-BF512 Datasheet, PDF (43/62 Pages) Analog Devices – Blackfin Embedded Processor

Preliminary Technical Data
ADSP-BF512/BF514/BF516/BF518 (F)
Timer Cycle Timing
Table 35 and Figure 24 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f_SCLK/2) MHz.
Table 35. Timer Cycle Timing
Parameter
Min
Max
Unit
Timing Characteristics
t_WL
Timer Pulse Width Input Low (Measured In SCLK Cycles)¹
t_WH
Timer Pulse Width Input High (Measured In SCLK Cycles)¹
t_TIS
Timer Input Setup Time Before CLKOUT Low²
t_TIH
Timer Input Hold Time After CLKOUT Low²
Switching Characteristics
1 × t_SCLK
ns
1 × t_SCLK
ns
5
ns
–2
ns
t_HTO
Timer Pulse Width Output (Measured In SCLK Cycles)
t_TOD
Timer Output Update Delay After CLKOUT High
1 × t_SCLK
(2³²â€“1)t_SCLK ns
8.1
ns
1 _{The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.}
2 _{Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.}
CLKOUT
TIMER OUTPUT
TIMER INPUT
t_TIS
t_TIH
t_WH, t_WL
Figure 24. Timer Cycle Timing
t_TOD
t_HTO
Rev. PrE | Page 43 of 62 | March 2009