ADSP-BF512 Datasheet, PDF (20/62 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF512/BF514/BF516/BF518 (F)
Preliminary Technical Data
SIGNAL DESCRIPTIONS
The processors’ signal definitions are listed in Table 9. In order
to maintain maximum function and reduce package size and
signal count, some signals have dual, multiplexed functions. In
cases where signal function is reconfigurable, the default state is
shown in plain text, while the alternate function is shown in
italics.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate.
All I/O signals have their input buffers disabled with the excep-
tion of the signals noted in the data sheet that need pull-ups or
pull downs if unused.
The SDA (serial data) and SCL (serial clock) pins/balls are open
drain and therefore require a pullup resistor. Consult version
2.1 of the I²C specification for the proper resistor value.
It is strongly advised to use the available IBIS models to ensure
that a given board design meets overshoot/undershoot and sig-
nal integrity requirements. If no IBIS simulation is performed, it
is strongly recommended to add series resistor terminations for
all Driver Types A, C and D. The termination resistors should
be placed near the processor to reduce transients and improve
signal integrity. The resistance value, typically 33 Ω or 47 Ω,
should be chosen to match the average board trace impedance.
Additionally, adding a parallel termination to CLKOUT may
prove useful in further enhancing signal integrity. Be sure to
verify overshoot/undershoot and signal integrity specifications
on actual hardware.
Table 9. Signal Descriptions
Signal Name
EBIU
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
AMS1–0
ARE
AWE
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Port F: GPIO and Multiplexed Peripherals
PF0/ETxD2/PPI D0/SPI1SEL2/TACLK6
PF1/ERxD2/PPI D1/PWM AH/TACLK7
PF2/ETxD3/PPI D2/PWM AL
PF3/ERxD3/PPI D3/PWM BH/TACLK0
PF4/ERxCLK/PPI D4/PWM BL/TACLK1
PF5/ERxDV/PPI D5/PWM CH/TACI0
PF6/COL/PPI D6/PWM CL/TACI1
PF7/SPI0SEL1/PPI D7/PWMSYNC
PF8/MDC/PPI D8/SPI1SEL4
PF9/MDIO/PPI D9/TMR2
Type Function
Driver
Type¹
O Address Bus
A
I/O Data Bus
A
O Byte Enable or Data Mask
A
O Bank Select
A
O Asynchronous Memory Read Enable
A
O Write Enable for Async
A
O SDRAM Row Address Strobe
A
O SDRAM Column Address Strobe
A
O SDRAM Write Enable
A
O SDRAM Clock Enable
A
O SDRAM Clock Output
B
O SDRAM A10 Signal
A
O SDRAM Bank Select
A
I/O GPIO/Ethernet MII Transmit D2/PPI Data 0/SPI1 Slave Select 2/Timer6 Alternate C
Clock
I/O GPIO/Ethernet MII Receive D2/PPI Data 1/PWM AH Output/Timer7 Alternate Clock C
I/O GPIO/Ethernet Transmit D3/PPI Data 2/PWM AL Output
C
I/O GPIO/Ethernet MII Data Receive D3/PPI Data 3/PWM BH Output/Timer0 Alternate C
Clock
I/O GPIO/Ethernet MII Receive Clock/PPI Data 4/PWM BL Out/Timer1 Alternate CLK C
I/O GPIO/Ethernet MII or RMII Receive Data Valid/PPI Data 5/PWM CH Out
C
/Timer0 Alternate Capture Input
I/O GPIO/Ethernet MII Collision/PPI Data 6/PWM CL Out/Timer1 Alternate Capture Input C
I/O GPIO/SPI0 Slave Select 1/PPI Data 7/PWM Sync
C
I/O GPIO/Ethernet Management Channel Clock/PPI Data 8/SPI1 Slave Select 4
C
I/O GPIO/Ethernet Management Channel Serial Data/PPI Data 9/Timer 2
C
Rev. PrE | Page 20 of 62 | March 2009