ADSP-BF539 Datasheet, PDF (42/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF539/ADSP-BF539F
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
DATA0 IS
SAMPLED
FRAME
SYNC IS
SAMPLED
FOR
DATA0
DATA1 IS
SAMPLED
t_SFSPE
t_HFSPE
Preliminary Technical Data
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
t_SDRPE t_HDRPE
Figure 20. PPI GP Rx Mode with External Frame Sync Timing
PPI_CLK
POLC = 0
PPI_CLK
POLC = 1
POLS = 1
PPI_FS1
POLS = 0
POLS = 1
PPI_FS2
POLS = 0
PPI_DATA
FRAME
SYNC IS
SAMPLED
DATA0 IS
DRIVEN
OUT
t_SFSPE
t_HFSPE
t_HDTPE
DATA0
Figure 21. PPI GP Tx Mode with External Frame Sync Timing
Rev. PrF | Page 42 of 68 | September 2006