ADSP-BF539 Datasheet, PDF (20/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
VDDINT (1.2 V)
FB
0.01 ␮F
ADSP-BF539F
MPIVDD
MTXON
0.1 ␮F
MXEGND
MTX
MRX
MRXON
5V
Power Gating Circuit
27 ⍀
5V
MOST FOT
Rx_Vdd
Tx_Vdd
TX_Data
RX_Data
Status
49.152 MHz Oscillator
CLKO
R1
220 ⍀
C1
0.1 ␮F
C2
0.01 ␮F
MXI
MXO
MLF
MXEGND
RFS0
MFS
MMCLK
MBCLK
TSCLK0
RSCLK0
DT0PRI
33 ⍀
33 ⍀
33 ⍀
L/RCLK
MCLK
BCLK
SDATA
Audio
DAC
MOST
Network
Audio
Channels
Figure 9. Example connections of ADSP-BF539/ADSP-BF539F to MOST Network
MXI driven with external Clock Oscillator IC (recommended)
• MXI should be driven with the clock output of a
49.152MHz or 45.1584MHz clock oscillator IC.
• MXO should be left unconnected.
• Avoid routing other switching signals near the oscillator
and clock output trace to avoid crosstalk. When not possi-
ble, shield traces with ground.
MXI/MXO with external Crystal
• The crystal must be a 49.152MHz or 45.1584MHz funda-
mental mode crystal.
• The crystal and load capacitors should be placed physically
close to the MXI and MXO pins on the board.
• The load capacitors should be grounded to MXEGND.
• The crystal and load capacitors should be wired up using
wide traces.
• Board trace capacitance on each lead should not be more
than 3pF.
• Trace capacitance plus load capacitance should equal the
load capacitance specification for the crystal.
• Avoid routing other switching signals near the crystal and
components to avoid crosstalk. When not possible, shield
traces and components with ground.
MXEGND - MXVR Crystal Oscillator and MXVR PLL Ground
• Should be routed with wide traces or as ground plane.
• Should be tied together to other board grounds at only one
point on the board.
• Avoid routing other switching signals near to MXEGND to
avoid crosstalk.
MXEVDD - MXVR Crystal Oscillator 3.3V Power
• Should be routed with wide traces or as power plane.
• Locally bypass MXEVDD with 0.1μF and 0.01μF decou-
pling capacitors to MXEGND.
• Avoid routing other switching signals near to MXEVDD to
avoid crosstalk.
MPIVDD - MXVR PLL 1.2V Power
• Should be routed with wide traces or as power plane.
• A ferrite bead should be placed between the 1.2V VDDINT
power plane and the MPIVDD pin for noise isolation.
• Locally bypass MPIVDD with 0.1μF and 0.01μF decou-
pling capacitors to MXEGND.
• Avoid routing other switching signals near to MPIVDD to
avoid crosstalk.
Fiber Optic Transceiver (FOT) Connections
• The traces between ADSP-BF539/ADSP-BF539F and the
FOT should be kept as short as possible.
• The receive data trace connecting the FOT Receive Data
output pin to the ADSP-BF539/ADSP-BF539F MRX input
pin should not have a series termination resistor. The edge
Rev. PrF | Page 20 of 68 | September 2006