ADSP-BF539 Datasheet, PDF (15/68 Pages) Analog Devices – Blackfin Embedded Processor

Preliminary Technical Data
this mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.
In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Table 5. Power Settings
Full On Enabled
No
Active
Enabled/ Disabled Yes
Sleep
Enabled
Deep Sleep Disabled
Hibernate Disabled
Enabled Enabled On
Enabled Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
Sleep Operating Mode—High Dynamic Power Savings
The Sleep mode reduces dynamic power dissipation by dis-
abling the clock to the processor core (CCLK). The PLL and
system clock (SCLK), however, continue to operate in this
mode. Typically an external event or RTC activity will wake up
the processor. When in the Sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL Control register (PLL_CTL). If BYPASS is disabled, the
processor will transition to the Full On mode. If BYPASS is
enabled, the processor will transition to the Active mode. When
in the Sleep mode, system DMA access to L1 memory is not
supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The Deep Sleep mode maximizes dynamic power savings by
disabling the clocks to the processor core (CCLK) and to all syn-
chronous peripherals (SCLK). Asynchronous peripherals such
as the RTC may still be running, but will not be able to access
internal resources or external memory. This powered down
mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in Deep Sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the Active mode.
Assertion of RESET while in Deep Sleep mode causes the pro-
cessor to transition to the Full On mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V_DDINT) to 0 V to provide the lowest static power
dissipation. Any critical information stored internally (memory
ADSP-BF539/ADSP-BF539F
contents, register contents, etc.) must be written to a non-vola-
tile storage device prior to removing power if the processor state
is to be preserved. Since V_DDEXT is still supplied in this mode, all
of the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up either by a Real
Time Clock wakeup, by CAN bus traffic, by asserting the RESET
pin, or by MOST bus traffic causing the MRXON pin to assert.
If either CAN or MXVR are not used, a general-purpose wake-
up is possible.
Power Savings
As shown in Table 6, the ADSP-BF539/ADSP-BF539F proces-
sor supports five different power domains. The use of multiple
power domains maximizes flexibility, while maintaining com-
pliance with industry standards and conventions.
• The VDDRTC 3.3V power domain supplies the RTC I/O
and logic so that the RTC can remain functional when the
rest of the chip is powered off.
• The MXEVDD 3.3V power domain supplies the MXVR
crystal and is separate to provide noise isolation.
• The MPIVDD 1.2V power domain supplies the MXVR
PLL and is separate to provide noise isolation.
• The VDDINT 1.2V power domain supplies all internal
logic except for the RTC logic and the MXVR PLL.
• The VDDEXT 3.3V power domain supplies all I/O except
for the RTC and MXVR crystals.
There are no sequencing requirements for the various power
domains.
Table 6. Power Domains
Power Domain
RTC crystal I/O and logic
MXVR crystal I/O
MXVR PLL analog and logic
All internal logic except RTC and MXVR PLL
All I/O except RTC and MXVR crystals
VDD Range
VDDRTC
MXEVDD
MPIVDD
VDDINT
VDDEXT
The RTCVDD should either be connected to an isolated supply
such as a battery (if the RTC is to operate while the rest of the
chip is powered down) or should be connected to the V_DDEXT
plane on the board. The RTCVDD should remain powered
when the processor is in hibernate state, and should also remain
powered even if the RTC functionality is not being used in an
application. The MXEVDD should be connected to the V_DDEXT
plane on the board at a single location with local bypass capaci-
tors. The MXEVDD should remain powered when the
processor is in hibernate state, and should also remain powered
even when the MXVR functionality is not being used in an
application. The MPIVDD should be connected to the V_DDINT
plane on the board at a single location through a ferrite bead
with local bypass capacitors.
Rev. PrF | Page 15 of 68 | September 2006