ADSP-21371_07 Datasheet, PDF (40/48 Pages) Analog Devices – SHARC® Processor

ADSP-21371
SPI Interface—Slave
Table 38. SPI Interface Protocol—Slave Switching and Timing Specifications
Parameter
Timing Requirements
t_SPICLKS
t_SPICHS
t_SPICLS
t_SDSCO
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
t_HDS
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
t_SSPIDS
Data Input Valid to SPICLK edge (Data Input Set-up Time)
t_HSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
t_SDPPW
SPIDS Deassertion Pulse Width (CPHASE=0)
Switching Characteristics
t_DSOE
t_DSDHI
t_DDSPIDS
t_HDSPIDS
t_DSOV
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHAS E = 0)
Min
4 × t_PCLK – 2
2 × t_PCLK – 2
2 × t_PCLK – 2
2 × t_PCLK
2 × t_PCLK
2 × t_PCLK
2
2
2 × t_PCLK
0
0
2 × t_PCLK
Max
6.8
6.8
9.5
5 × t_PCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
t_SDSCO
SPICLK
(CP = 1)
(INPUT)
t_DSOE
t_{SPIC HS}
t_SPICLS
t_DDSPIDS
t_SPICLS
t_SPICHS
t_SPICLKS
t_HDS
t_DDSPIDS
MISO
(OUTPUT)
CPHASE = 1
MOSI
(INPUT)
t_SSPIDS
MISO
(OUTPUT) _{t D S OV}
CPHASE = 0
MSB
MSB
MSB VALID
t_DDSPIDS
MOSI
(INPUT)
MSB VALID
t_SSPIDS
LSB
t_HSPIDS
LSB VALID
t_HDSPIDS
LSB
t_SSPIDS
t_HSPIDS
LSB VALID
t_SDPPW
t_DSDHI
t_HDSPIDS
t_DSDHI
Figure 30. SPI Slave Timing
Rev. 0 | Page 40 of 48 | June 2007