ADSP-21371_07 Datasheet, PDF (1/48 Pages) Analog Devices – SHARC® Processor

SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—1M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21371 is available with a 266 MHz core instruction
rate with unique audiocentric peripherals such as the digi­
tal applications interface, serial ports, precision clock
generators, and more. For complete ordering information,
see Ordering Guide on Page 48.
SHARC^® Processor
ADSP-21371
CORE PRO CESSOR
TI ME RS
INSTRUCTIO N
CACHE
32 Ï«48 -BIT
DAG1
8 Ï« 4 Ï« 32
DAG2
8 Ï« 4 Ï« 32
P ROGRAM
SE QUENCER
P M A D D RE SS BU S 32
DM A DD R ES S B U S
32
PM DA TA B U S 6 4
DM DATA BUS ⁶⁴
PROCESS ING
E LE M ENT
(P EX)
PROCESS ING
ELE ME NT
(P EY)
PX REGISTER
4 BLOCKS O F
ON-CHIP MEMORY
1M BIT RAM, 4M BIT ROM
JTAG TEST & EMULATIO N
PWM
ADDR
32
DATA
64
IO A(2 4)
FLAGS4-15
I OD(3 2)
EXTERNAL PORT
7
SDRAM
CONTRO LLER
ASY NCHRONOUS
3
MEMO RY
INTERFACE
32
DATA
11
CONTROL
24
ADDRES S
IOP REGISTER (MEMORY MAPPED)
CONTROL, STATUS, & DATA BUFFERS
DMA CONTROLLER
(30 CHANNELS)
MEMO RY-TO-MEMORY
DMA (2)
4 _{GPIO FLAGS/}
IRQ/TIM EX P
S
PRECISION CLOCK
G ENERATORS (4)
S/PDIF (RX/TX)
SERIAL PORTS (8)
INPUT DATA POR T/
PDAP
DAI PINS
DIGITAL APPLICATIONS INTERFACE
20
SPI PORT (2)
TWO WIRE
INTERFACE
DPI PINS
UART (1)
TIMERS (2)
DIGITAL PERIP HERAL INTE RFACE
I/O PROCESSOR
14
Figure 1. Functional Block Diagram
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Rev. 0
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