ADSP-21371_07 Datasheet, PDF (33/48 Pages) Analog Devices – SHARC® Processor

ADSP-21371
Input Data Port (IDP)
The timing requirements for the IDP are given in Table 31. IDP
signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1
pins using the SRU. Therefore, the timing specifications pro­
vided below are valid at the DAI_P20–1 pins.
Table 31. Input Data Port (IDP)
Parameter
Min
Max
Unit
Timing Requirements
t_SISFS ¹
FS Setup Before SCLK Rising Edge
3.8
ns
t_SIHFS¹
FS Hold After SCLK Rising Edge
2.5
ns
t_SISD¹
SData Setup Before SCLK Rising Edge
2.5
ns
t_SIHD¹
SData Hold After SCLK Rising Edge
2.5
ns
t_IDPCLKW
t_IDPCLK
Clock Width
Clock Period
9
ns
24
ns
1 _{DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.}
DAI_P20-1
(SCLK)
DAI_P20-1
(FS)
DAI_P20-1
(SDATA)
t_IPDCLKW
SAMPLE EDGE
t_IPDCLK
t_SISFS
t_SIHFS
t_SISD
t_SIHD
Figure 21. IDP Master Timing
Rev. 0 | Page 33 of 48 | June 2007