DAC888_15 Datasheet, PDF (4/12 Pages) Analog Devices – 8-BIt LevelTriggered Latch

IPMI)
DAC-888 BYTEDAC~ 8-BIT HIGH-SPEED "MICROPROCESSOR COMPATIBLE" MULTIPLYING D/A CONVERTER
DICE CHARACTERISTICS
1. DB7 (MSB)
2. DB6
3. DB5
4. DB4
5. DB3
6. DB2
7. DB1
8. DBO (LSB)
9. GROUND
10. VREF (+)
11. VREFt-)
12. COMP
13. lOUT
14. lOUT
15. V-
16. WR
17. CE
18. V+
DIE SIZE 0.141 X 0.127 inch, 17,907 sq. mils
(3.58 X 3.23 mm, 11.56 sq. mm)
For additional DICE ordering information,
refer to 1990/91 Data Book, Section 2.
OBSOLETE WAFER TEST LIMITS at Vs= +5, -12V, 'REF= 2mA, TA= 25°C, unless otherwise noted. Output characteristics refer to both
lOUTand lOUT
PARAMETER
Resolution
Monotonicity
Nonlinearity
Output Voltage
Compliance
Full Range Current
Full Range Symmetry
SYMBOL
CONDITIONS
VOG
IFR14
I FRS
Full-Scale Current
Change < 1/2 LSB
ROUT> 20M!! Typ.
VREF= 10.000V
R 11' R 10= 5.000k!!
TA = 25°C
IFR14-IFR13
DAC-888N
LIMIT
8
8
:to.1
+5
5
204
1.94
:!::8
DAC-888G
LIMIT
8
8
:to.19
+5
-5
204
1.94
:!::8
UNITS
Bits MIN
Bits MIN
%FS MAX
VMAX
V MIN
mA MAX
mA MIN
}J.A MAX
Zero-Scale Current
Izs
2
2
}J.A MAX
Output Current Range
I FSR
IREF = 3mA
21
2.1
mA MIN
Reference Bias Current
Power Supply
Sensitivity
Power Supply
Current
16
PSSI FR,
PSSI FR
1+
1-
V+ = 4.5V to 5.5V
V-=-10.8Vto~132V,
IREF = 2mA
IREF= 1mA
3
:!::0.01
:to.0-1-
16
9
3
}J.A MAX
:!::0.01 _{%.J.I Fs/%.J. V + MAX}
,,:0.01 _{%.J./FS/%.J.V-' MAX}
16
mA MAX
9
Power Dissipation
Pd
I REF= 2mA
190
190
mW MAX
Logic Input Levels
Logic Input "0"
V,L
Logic Input "1"
V'H
0.8
0.8
V MAX
2
2
V MIN
I'L
V,N = OV
Logic Input Current
I'H
V'N = 5.25V
- 10
10
1
----...-
}J.AMAX
1
NOTE:
Electrical tests are performed at wafer probe
guaranteed for standard product dice. Consult
to the limits shown.
factory to negotiate
Due to variations in assembly methods and normal yield loss, yield after packaging is not
specifications based on dice lot qualification through sample lot assembly and testing.
TYPICAL ELECTRICAL CHARACTERISTICS V+ = +5V, -12V, 'REF = 2mA, TA = 25°C, unless otherwise noted.
PARAMETER
Reference Input Slew Rate
Settling Time
--
-D--a--ta- ^{Input Setup Time}
Data Input _-H_--o_--l_-d_------T_--i_-m_---e_----
Chip Enable
Write Pulse Width
~
SYMBOL
dlldt
IS
tos
toH
tENW
.
-
~-
- -~
CONDITIONS
From CE Negative Edge to :t 1/2 LSB,
All bits Switched ON or OFF
-....--.-.-------------------.------------------
11-104
--~
DAC-888
TYPICAL
8.0
300
UNITS
mA/}J.s
ns
-------------
100
ns
0
ns
200
ns
7/89, Rev. B