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CN-0279 Datasheet, PDF (4/5 Pages) Analog Devices – High IF Sampling Receiver Front End with Band-Pass Filter
CN-0279
Circuit Optimization Techniques and Trade-Offs
The parameters in this interface circuit are very interactive;
therefore, it is almost impossible to optimize the circuit for all
key specifications (bandwidth, bandwidth flatness, SNR, SFDR,
and gain). However, the peaking, which often occurs in the
bandwidth response, can be minimized by varying RA and RKB.
The value of RA also affects SNR performance. Larger values,
while reducing the bandwidth peaking, tend to slightly increase
the SNR because of the higher signal level required to drive the
ADC full scale.
Select the RKB series resistor on the ADC inputs to minimize
distortion caused by any residual charge injection from the
internal sampling capacitor within the ADC. Increasing this
resistor also tends to reduce bandwidth peaking.
However, increasing RKB increases signal attenuation, and the
amplifier must drive a larger signal to fill the ADC input range.
For optimizing center frequency, pass-band characteristics, the
series capacitor, CAAF2, can be varied by a small amount.
Normally, the ADC input termination resistor, RTADC, is selected
to make the net ADC input impedance between 200 Ω and 400 Ω,
which is typical of most amplifier characteristic load values. Using
too high or too low a value can have an adverse effect on the
linearity of the amplifier.
Balancing these trade-offs can be somewhat difficult. In this
design, each parameter was given equal weight; therefore, the
values chosen are representative of the interface performance
for all the design characteristics. In some designs, different values
can be chosen to optimize SFDR, SNR, or input drive level,
depending on system requirements.
The SFDR performance in this design is determined by two
factors: the amplifier and ADC interface component values, as
shown in Figure 1.
Note that the signal in this design is ac-coupled with the 0.1 µF
capacitors to block the common-mode voltages between the
amplifier, its termination resistors, and the ADC inputs. Refer to
the AD9642 data sheet for further details regarding common-
mode voltages.
Circuit Note
Passive Component and PC Board Parasitic Considerations
The performance of this or any high speed circuit is highly
dependent on proper printed circuit board (PCB) layout. This
includes, but is not limited to, power supply bypassing, controlled
impedance lines (where required), component placement, signal
routing, and power and ground planes. See Tutorial MT-031 and
Tutorial MT-101 for more detailed information regarding PCB
layout for high speed ADCs and amplifiers. In addition, see the
CN-0227 and the CN-0238.
Use low parasitic surface-mount capacitors, inductors, and resistors
for the passive components in the filter. The inductors chosen
are from the Coilcraft 0603CS series. The surface-mount capacitors
used in the filter are 5%, C0G, 0402 type for stability and accuracy.
See the CN-0279 Design Support Package for the complete
documentation on the system.
COMMON VARIATIONS
The AD9643 is a dual version of the AD9642.
For lower power and bandwidth, the ADA4950-1 and/or
ADL5561/ADL5562 can also be used. These devices are pin
compatible with the other singles previously listed.
CIRCUIT EVALUATION AND TEST
This circuit uses a modified AD9642-250EBZ circuit board and
the HSC-ADC-EVALCZ FPGA-based data capture board. The
two boards have mating high speed connectors, allowing for the
quick setup and evaluation of the performance of the circuit. The
modified AD9642-250EBZ board contains the circuit evaluated
as described in this note, and the HSC-ADC-EVALCZ data
capture board is used in conjunction with VisualAnalog® evaluation
software, as well as the SPI Controller software to properly control
the ADC and capture the data. See User Guide UG-386 for the
schematics, BOM, and layout for the AD9642-250EBZ board.
The readme.txt file in the CN-0279 Design Support Package
describes the modifications made to the standard AD9642-250EBZ
board. Application Note AN-835 contains complete details on
how to set up the hardware and software to run the tests described
in this circuit note.
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