CN-0279 Datasheet, PDF (3/5 Pages) Analog Devices – High IF Sampling Receiver Front End with Band-Pass Filter

Circuit Note
CN-0279
ANALOG
INPUT
INPUT
Z = 50Ω
Z = R_I/2
XFMR
1:2 Z
0.1µF
0.1µF
AVDD_AMP
R_A ^0.1µF
C_AAF2 L_AAF1
Z_O/2
R_I
GAIN
Z_O/2
C_AAF1
L_AAF
L_AAF
R_TADC
0.1µF
R_TADC
R_{A 0.1µF}
C_AAF2 ^LAAF1
AVDD DRVDD
R_KB
C_AAF3
R_ADC
R_KB
ADC
INTERNAL
INPUT Z
C_ADC
INTERNAL
INPUT Z
Z_AL
Z_AAFS
Z_AAFL
VCM
Figure 5. Generalized Differential Amplifier/ADC Interface with Band-Pass Filter
Filter and Interface Design Procedure
6. Calculate the filter source resistance by
In this section, a general approach to the design of the amplifier/
ADC interface with a band-pass filter is presented. To achieve
optimum performance (bandwidth, SNR, and SFDR), there are
certain design constraints placed on the general circuit by the
amplifier and the ADC.
1. The amplifier must see the correct dc load recommended
by the data sheet for optimum performance.
2. The correct amount of series resistance must be used between
the amplifier and the load presented by the filter. This is to
prevent undesired peaking in the pass band.
3. The input to the ADC must be reduced by external parallel
resistors, and the correct series resistance must be used to
isolate the ADC from the filter. This series resistor also
reduces peaking.
The generalized circuit shown in Figure 5 applies to most high
speed differential amplifier/ADC interfaces and was used as a
basis for the band-pass filter. This design approach tends to
minimize the insertion loss of the filter by taking advantage of
the relatively high input impedance of most high speed ADCs
and the relatively low impedance of the driving source (amplifier).
The basic design process is as follows:
1. Set the external ADC termination resistors, R_TADC , so that
the parallel combination of R_TADC and R_ADC is between
200 Ω and 400 Ω.
2. Select R_KB based on experience and/or the ADC data sheet
recommendations, typically between 5 Ω and 36 Ω.
3. Calculate the filter load impedance using
Z_AAFL = 2R_TADC || (R_ADC + 2R_KB)
4. Select the amplifier external series resistor, R_A. Make R_A
less than 10 Ω if the amplifier differential output impedance
is 100 Ω to 200 Ω. Make R_A between 5 Ω and 36 Ω if the
output impedance of the amplifier is 12 Ω or less.
5. Select Z_AAFL so that the total load seen by the amplifier, Z_AL,
is optimum for the particular differential amplifier chosen
using the following equation:
Z_AAFS = Z_O + 2R_A
7. Using a filter design program or tables design the filter
using the source and load impedances, Z_AAFS and Z_AAFL, type
of filter, bandwidth, and order. Use a bandwidth that is about
10% higher than the desired bandwidth of the application
pass band to ensure flatness in the frequency span.
After running these preliminary calculations, the circuit must
be given a quick review for the following items.
1. The value of C_AAF3 must be at least 10 pF so that it is several
times larger than C_ADC. This minimizes the sensitivity of
the filter to variations in C_ADC.
2. The ratio of Z_AAFL to Z_AAFS must not be more than about 7 so
that the filter is within the limits of most filter tables and
design programs.
3. The value of C_AAF1 must be at least 5 pF to minimize sensitivity
to parasitic capacitance and component variations.
4. The inductor, L_AAF, must be a reasonable value of at least
several nH.
5. The value of C_AFF2 and L_AAF1 must be reasonable values.
Sometimes circuit simulators can make these values too
low or too high. To make these values more reasonable,
simply ratio these values with better standard value
components that maintain the same resonant frequency.
In some cases, the filter design program can provide more than
one unique solution, especially with higher order filters. The
solution that uses the most reasonable set of component values
should always be chosen. Also, choose a configuration that ends
in a shunt capacitor so that it can be combined with the ADC
input capacitance.
Z_AL = 2R_A + Z_AAFL
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