ADSP-21267 Datasheet, PDF (4/44 Pages) Analog Devices – Preliminary Technical Data

ADSP-21267
PRELIMINARY TECHNICAL DATA
C LOC K
2
2
3
A DC
(OPTI ONAL)
CLK
FS
S DAT
DAC
(OP TIONAL)
CLK
FS
S DAT
C L K IN
X TAL
C L K _C F G1- 0
BOOTCFG1 -0
FLG3 -1
ADSP-21267
CL K OU T
ALE
AD1 5-0
RD
WR
FLG 0
D A I_P1
DAI_ P2
DAI_ P3
DAI_P 18
DAI _P 19
DAI_ P2 0
SR U
S CLK0
S FS0
S D0A
S D0B
SPO RT0
S PORT1
SP ORT2
SP ORT 3
L A T CH
A DD R
D AT A
OE
WE
CS
PA R A L L EL
POR T
RAM , ROM
BOO T ROM
I /O DEVI CE
DAI
RES ET
CLK
FS
P CG A
PC GB
JT A G
6
Figure 2. ADSP-21267 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multi-function instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general purpose data register file is contained in each process-
ing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21267 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see the Figure 1 on page 1). With the ADSP-21267’s separate
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction Cache
TheADSP-21267 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates and FFT butterfly
processing.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21267’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
Rev. PrA | Page 4 of 44 | January 2004